b533f8ae79
Make the interrupt numbers match the OpenPIC spec intead of the Freescale docs which distinguish between internal and external interrupts. Now we can use the interrupt number directly to find the register offset associated with it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
153 lines
3.3 KiB
Plaintext
153 lines
3.3 KiB
Plaintext
/*
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* MPC8544 DS Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8544DS";
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compatible = "MPC8544DS", "MPC85xxDS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#cpus = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8544@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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32-bit;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 00000000>; // Filled by U-Boot
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};
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soc8544@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00100000>; // CCSRBAR 1M
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bus-frequency = <0>; // Filled out by uboot.
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memory-controller@2000 {
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compatible = "fsl,8544-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <12 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8544-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <10 2>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <a 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <a 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <26000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1f 2 20 2 21 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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built-in;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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};
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};
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