c97c5aa83c
The RealView PBX board has two 512MB blocks of memory - one at 0x70000000 (with 256MB mirror at 0) and another at 0x20000000. Only the block at 0x70000000 (or the mirror at 0) may be used for DMA (e.g. framebuffer). This patch adds the sparsemem definitions to allow the use of all the memory split as follows: 256MB @ 0x00000000 (ZONE_DMA) 512MB @ 0x20000000 (ZONE_NORMAL) 256MB @ 0x80000000 (ZONE_NORMAL) Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
831 lines
19 KiB
C
831 lines
19 KiB
C
/*
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* linux/arch/arm/mach-realview/core.c
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*
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* Copyright (C) 1999 - 2003 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/clcd.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/smsc911x.h>
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#include <linux/ata_platform.h>
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#include <linux/amba/mmci.h>
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#include <asm/clkdev.h>
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#include <asm/system.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/leds.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/icst307.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/gic.h>
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#include <mach/platform.h>
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#include <mach/irqs.h>
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#include "core.h"
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#include "clock.h"
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#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
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/* used by entry-macro.S and platsmp.c */
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void __iomem *gic_cpu_base_addr;
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#ifdef CONFIG_ZONE_DMA
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/*
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* Adjust the zones if there are restrictions for DMA access.
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*/
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void __init realview_adjust_zones(int node, unsigned long *size,
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unsigned long *hole)
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{
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unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
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if (!machine_is_realview_pbx() || node || (size[0] <= dma_size))
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return;
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size[ZONE_NORMAL] = size[0] - dma_size;
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size[ZONE_DMA] = dma_size;
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hole[ZONE_NORMAL] = hole[0];
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hole[ZONE_DMA] = 0;
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}
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#endif
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/*
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* This is the RealView sched_clock implementation. This has
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* a resolution of 41.7ns, and a maximum value of about 179s.
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long long v;
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v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
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do_div(v, 3);
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return v;
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}
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#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
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static int realview_flash_init(void)
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{
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u32 val;
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val = __raw_readl(REALVIEW_FLASHCTRL);
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val &= ~REALVIEW_FLASHPROG_FLVPPEN;
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__raw_writel(val, REALVIEW_FLASHCTRL);
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return 0;
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}
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static void realview_flash_exit(void)
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{
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u32 val;
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val = __raw_readl(REALVIEW_FLASHCTRL);
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val &= ~REALVIEW_FLASHPROG_FLVPPEN;
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__raw_writel(val, REALVIEW_FLASHCTRL);
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}
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static void realview_flash_set_vpp(int on)
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{
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u32 val;
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val = __raw_readl(REALVIEW_FLASHCTRL);
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if (on)
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val |= REALVIEW_FLASHPROG_FLVPPEN;
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else
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val &= ~REALVIEW_FLASHPROG_FLVPPEN;
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__raw_writel(val, REALVIEW_FLASHCTRL);
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}
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static struct flash_platform_data realview_flash_data = {
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.map_name = "cfi_probe",
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.width = 4,
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.init = realview_flash_init,
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.exit = realview_flash_exit,
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.set_vpp = realview_flash_set_vpp,
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};
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struct platform_device realview_flash_device = {
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.name = "armflash",
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.id = 0,
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.dev = {
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.platform_data = &realview_flash_data,
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},
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};
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int realview_flash_register(struct resource *res, u32 num)
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{
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realview_flash_device.resource = res;
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realview_flash_device.num_resources = num;
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return platform_device_register(&realview_flash_device);
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}
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static struct smsc911x_platform_config smsc911x_config = {
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.flags = SMSC911X_USE_32BIT,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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.phy_interface = PHY_INTERFACE_MODE_MII,
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};
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static struct platform_device realview_eth_device = {
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.name = "smsc911x",
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.id = 0,
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.num_resources = 2,
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};
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int realview_eth_register(const char *name, struct resource *res)
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{
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if (name)
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realview_eth_device.name = name;
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realview_eth_device.resource = res;
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if (strcmp(realview_eth_device.name, "smsc911x") == 0)
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realview_eth_device.dev.platform_data = &smsc911x_config;
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return platform_device_register(&realview_eth_device);
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}
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struct platform_device realview_usb_device = {
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.name = "isp1760",
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.num_resources = 2,
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};
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int realview_usb_register(struct resource *res)
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{
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realview_usb_device.resource = res;
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return platform_device_register(&realview_usb_device);
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}
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static struct pata_platform_info pata_platform_data = {
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.ioport_shift = 1,
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};
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static struct resource pata_resources[] = {
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[0] = {
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.start = REALVIEW_CF_BASE,
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.end = REALVIEW_CF_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = REALVIEW_CF_BASE + 0x100,
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.end = REALVIEW_CF_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device realview_cf_device = {
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.name = "pata_platform",
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.id = -1,
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.num_resources = ARRAY_SIZE(pata_resources),
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.resource = pata_resources,
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.dev = {
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.platform_data = &pata_platform_data,
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},
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};
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static struct resource realview_i2c_resource = {
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.start = REALVIEW_I2C_BASE,
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.end = REALVIEW_I2C_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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};
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struct platform_device realview_i2c_device = {
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.name = "versatile-i2c",
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.id = 0,
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.num_resources = 1,
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.resource = &realview_i2c_resource,
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};
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static struct i2c_board_info realview_i2c_board_info[] = {
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{
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I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
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},
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};
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static int __init realview_i2c_init(void)
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{
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return i2c_register_board_info(0, realview_i2c_board_info,
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ARRAY_SIZE(realview_i2c_board_info));
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}
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arch_initcall(realview_i2c_init);
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#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
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/*
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* This is only used if GPIOLIB support is disabled
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*/
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static unsigned int realview_mmc_status(struct device *dev)
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{
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struct amba_device *adev = container_of(dev, struct amba_device, dev);
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u32 mask;
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if (adev->res.start == REALVIEW_MMCI0_BASE)
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mask = 1;
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else
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mask = 2;
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return readl(REALVIEW_SYSMCI) & mask;
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}
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struct mmci_platform_data realview_mmc0_plat_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = realview_mmc_status,
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.gpio_wp = 17,
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.gpio_cd = 16,
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};
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struct mmci_platform_data realview_mmc1_plat_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = realview_mmc_status,
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.gpio_wp = 19,
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.gpio_cd = 18,
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};
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/*
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* Clock handling
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*/
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static const struct icst307_params realview_oscvco_params = {
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.ref = 24000,
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.vco_max = 200000,
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.vd_min = 4 + 8,
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.vd_max = 511 + 8,
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.rd_min = 1 + 2,
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.rd_max = 127 + 2,
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};
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static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
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{
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void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
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void __iomem *sys_osc;
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u32 val;
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if (machine_is_realview_pb1176())
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sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
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else
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sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
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val = readl(sys_osc) & ~0x7ffff;
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val |= vco.v | (vco.r << 9) | (vco.s << 16);
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writel(0xa05f, sys_lock);
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writel(val, sys_osc);
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writel(0, sys_lock);
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}
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static struct clk oscvco_clk = {
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.params = &realview_oscvco_params,
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.setvco = realview_oscvco_set,
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};
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/*
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* These are fixed clocks.
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*/
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static struct clk ref24_clk = {
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.rate = 24000000,
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};
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static struct clk_lookup lookups[] = {
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{ /* UART0 */
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.dev_id = "dev:uart0",
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.clk = &ref24_clk,
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}, { /* UART1 */
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.dev_id = "dev:uart1",
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.clk = &ref24_clk,
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}, { /* UART2 */
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.dev_id = "dev:uart2",
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.clk = &ref24_clk,
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}, { /* UART3 */
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.dev_id = "fpga:uart3",
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.clk = &ref24_clk,
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}, { /* KMI0 */
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.dev_id = "fpga:kmi0",
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.clk = &ref24_clk,
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}, { /* KMI1 */
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.dev_id = "fpga:kmi1",
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.clk = &ref24_clk,
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}, { /* MMC0 */
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.dev_id = "fpga:mmc0",
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.clk = &ref24_clk,
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}, { /* EB:CLCD */
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.dev_id = "dev:clcd",
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.clk = &oscvco_clk,
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}, { /* PB:CLCD */
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.dev_id = "issp:clcd",
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.clk = &oscvco_clk,
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}
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};
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static int __init clk_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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return 0;
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}
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arch_initcall(clk_init);
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/*
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* CLCD support.
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*/
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#define SYS_CLCD_NLCDIOON (1 << 2)
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#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
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#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
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#define SYS_CLCD_ID_MASK (0x1f << 8)
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#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
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#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
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#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
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#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
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#define SYS_CLCD_ID_VGA (0x1f << 8)
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static struct clcd_panel vga = {
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.mode = {
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.name = "VGA",
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.refresh = 60,
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.xres = 640,
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.yres = 480,
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.pixclock = 39721,
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.left_margin = 40,
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.right_margin = 24,
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.upper_margin = 32,
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.lower_margin = 11,
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.hsync_len = 96,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel xvga = {
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.mode = {
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.name = "XVGA",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15748,
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.left_margin = 152,
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.right_margin = 48,
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.upper_margin = 23,
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.lower_margin = 3,
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.hsync_len = 104,
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.vsync_len = 4,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel sanyo_3_8_in = {
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.mode = {
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.name = "Sanyo QVGA",
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.refresh = 116,
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.xres = 320,
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.yres = 240,
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.pixclock = 100000,
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.left_margin = 6,
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.right_margin = 6,
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.upper_margin = 5,
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.lower_margin = 5,
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.hsync_len = 6,
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.vsync_len = 6,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD,
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.cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel sanyo_2_5_in = {
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.mode = {
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.name = "Sanyo QVGA Portrait",
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.refresh = 116,
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.xres = 240,
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.yres = 320,
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.pixclock = 100000,
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.left_margin = 20,
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.right_margin = 10,
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.upper_margin = 2,
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.lower_margin = 2,
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.hsync_len = 10,
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.vsync_len = 2,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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static struct clcd_panel epson_2_2_in = {
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.mode = {
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.name = "Epson QCIF",
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.refresh = 390,
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.xres = 176,
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.yres = 220,
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.pixclock = 62500,
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.left_margin = 3,
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.right_margin = 2,
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.upper_margin = 1,
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.lower_margin = 0,
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.hsync_len = 3,
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.vsync_len = 2,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED,
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},
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.width = -1,
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.height = -1,
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.tim2 = TIM2_BCD | TIM2_IPC,
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.cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
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.bpp = 16,
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};
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/*
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* Detect which LCD panel is connected, and return the appropriate
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* clcd_panel structure. Note: we do not have any information on
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* the required timings for the 8.4in panel, so we presently assume
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* VGA timings.
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*/
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static struct clcd_panel *realview_clcd_panel(void)
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{
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void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
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struct clcd_panel *vga_panel;
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struct clcd_panel *panel;
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u32 val;
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if (machine_is_realview_eb())
|
|
vga_panel = &vga;
|
|
else
|
|
vga_panel = &xvga;
|
|
|
|
val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
|
|
if (val == SYS_CLCD_ID_SANYO_3_8)
|
|
panel = &sanyo_3_8_in;
|
|
else if (val == SYS_CLCD_ID_SANYO_2_5)
|
|
panel = &sanyo_2_5_in;
|
|
else if (val == SYS_CLCD_ID_EPSON_2_2)
|
|
panel = &epson_2_2_in;
|
|
else if (val == SYS_CLCD_ID_VGA)
|
|
panel = vga_panel;
|
|
else {
|
|
printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
|
|
val);
|
|
panel = vga_panel;
|
|
}
|
|
|
|
return panel;
|
|
}
|
|
|
|
/*
|
|
* Disable all display connectors on the interface module.
|
|
*/
|
|
static void realview_clcd_disable(struct clcd_fb *fb)
|
|
{
|
|
void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
|
|
u32 val;
|
|
|
|
val = readl(sys_clcd);
|
|
val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
|
|
writel(val, sys_clcd);
|
|
}
|
|
|
|
/*
|
|
* Enable the relevant connector on the interface module.
|
|
*/
|
|
static void realview_clcd_enable(struct clcd_fb *fb)
|
|
{
|
|
void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
|
|
u32 val;
|
|
|
|
/*
|
|
* Enable the PSUs
|
|
*/
|
|
val = readl(sys_clcd);
|
|
val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
|
|
writel(val, sys_clcd);
|
|
}
|
|
|
|
static int realview_clcd_setup(struct clcd_fb *fb)
|
|
{
|
|
unsigned long framesize;
|
|
dma_addr_t dma;
|
|
|
|
if (machine_is_realview_eb())
|
|
/* VGA, 16bpp */
|
|
framesize = 640 * 480 * 2;
|
|
else
|
|
/* XVGA, 16bpp */
|
|
framesize = 1024 * 768 * 2;
|
|
|
|
fb->panel = realview_clcd_panel();
|
|
|
|
fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
|
|
&dma, GFP_KERNEL | GFP_DMA);
|
|
if (!fb->fb.screen_base) {
|
|
printk(KERN_ERR "CLCD: unable to map framebuffer\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
fb->fb.fix.smem_start = dma;
|
|
fb->fb.fix.smem_len = framesize;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
|
|
{
|
|
return dma_mmap_writecombine(&fb->dev->dev, vma,
|
|
fb->fb.screen_base,
|
|
fb->fb.fix.smem_start,
|
|
fb->fb.fix.smem_len);
|
|
}
|
|
|
|
static void realview_clcd_remove(struct clcd_fb *fb)
|
|
{
|
|
dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
|
|
fb->fb.screen_base, fb->fb.fix.smem_start);
|
|
}
|
|
|
|
struct clcd_board clcd_plat_data = {
|
|
.name = "RealView",
|
|
.check = clcdfb_check,
|
|
.decode = clcdfb_decode,
|
|
.disable = realview_clcd_disable,
|
|
.enable = realview_clcd_enable,
|
|
.setup = realview_clcd_setup,
|
|
.mmap = realview_clcd_mmap,
|
|
.remove = realview_clcd_remove,
|
|
};
|
|
|
|
#ifdef CONFIG_LEDS
|
|
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
|
|
|
|
void realview_leds_event(led_event_t ledevt)
|
|
{
|
|
unsigned long flags;
|
|
u32 val;
|
|
u32 led = 1 << smp_processor_id();
|
|
|
|
local_irq_save(flags);
|
|
val = readl(VA_LEDS_BASE);
|
|
|
|
switch (ledevt) {
|
|
case led_idle_start:
|
|
val = val & ~led;
|
|
break;
|
|
|
|
case led_idle_end:
|
|
val = val | led;
|
|
break;
|
|
|
|
case led_timer:
|
|
val = val ^ REALVIEW_SYS_LED7;
|
|
break;
|
|
|
|
case led_halted:
|
|
val = 0;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
writel(val, VA_LEDS_BASE);
|
|
local_irq_restore(flags);
|
|
}
|
|
#endif /* CONFIG_LEDS */
|
|
|
|
/*
|
|
* Where is the timer (VA)?
|
|
*/
|
|
void __iomem *timer0_va_base;
|
|
void __iomem *timer1_va_base;
|
|
void __iomem *timer2_va_base;
|
|
void __iomem *timer3_va_base;
|
|
|
|
/*
|
|
* How long is the timer interval?
|
|
*/
|
|
#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
|
|
#if TIMER_INTERVAL >= 0x100000
|
|
#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
|
|
#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
|
|
#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
|
|
#elif TIMER_INTERVAL >= 0x10000
|
|
#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
|
|
#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
|
|
#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
|
|
#else
|
|
#define TIMER_RELOAD (TIMER_INTERVAL)
|
|
#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
|
|
#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
|
|
#endif
|
|
|
|
static void timer_set_mode(enum clock_event_mode mode,
|
|
struct clock_event_device *clk)
|
|
{
|
|
unsigned long ctrl;
|
|
|
|
switch(mode) {
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
|
writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
|
|
|
|
ctrl = TIMER_CTRL_PERIODIC;
|
|
ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
|
|
break;
|
|
case CLOCK_EVT_MODE_ONESHOT:
|
|
/* period set, and timer enabled in 'next_event' hook */
|
|
ctrl = TIMER_CTRL_ONESHOT;
|
|
ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
|
|
break;
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
default:
|
|
ctrl = 0;
|
|
}
|
|
|
|
writel(ctrl, timer0_va_base + TIMER_CTRL);
|
|
}
|
|
|
|
static int timer_set_next_event(unsigned long evt,
|
|
struct clock_event_device *unused)
|
|
{
|
|
unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
|
|
|
|
writel(evt, timer0_va_base + TIMER_LOAD);
|
|
writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clock_event_device timer0_clockevent = {
|
|
.name = "timer0",
|
|
.shift = 32,
|
|
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
|
.set_mode = timer_set_mode,
|
|
.set_next_event = timer_set_next_event,
|
|
.rating = 300,
|
|
.cpumask = cpu_all_mask,
|
|
};
|
|
|
|
static void __init realview_clockevents_init(unsigned int timer_irq)
|
|
{
|
|
timer0_clockevent.irq = timer_irq;
|
|
timer0_clockevent.mult =
|
|
div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
|
|
timer0_clockevent.max_delta_ns =
|
|
clockevent_delta2ns(0xffffffff, &timer0_clockevent);
|
|
timer0_clockevent.min_delta_ns =
|
|
clockevent_delta2ns(0xf, &timer0_clockevent);
|
|
|
|
clockevents_register_device(&timer0_clockevent);
|
|
}
|
|
|
|
/*
|
|
* IRQ handler for the timer
|
|
*/
|
|
static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct clock_event_device *evt = &timer0_clockevent;
|
|
|
|
/* clear the interrupt */
|
|
writel(1, timer0_va_base + TIMER_INTCLR);
|
|
|
|
evt->event_handler(evt);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static struct irqaction realview_timer_irq = {
|
|
.name = "RealView Timer Tick",
|
|
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
|
.handler = realview_timer_interrupt,
|
|
};
|
|
|
|
static cycle_t realview_get_cycles(struct clocksource *cs)
|
|
{
|
|
return ~readl(timer3_va_base + TIMER_VALUE);
|
|
}
|
|
|
|
static struct clocksource clocksource_realview = {
|
|
.name = "timer3",
|
|
.rating = 200,
|
|
.read = realview_get_cycles,
|
|
.mask = CLOCKSOURCE_MASK(32),
|
|
.shift = 20,
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
|
};
|
|
|
|
static void __init realview_clocksource_init(void)
|
|
{
|
|
/* setup timer 0 as free-running clocksource */
|
|
writel(0, timer3_va_base + TIMER_CTRL);
|
|
writel(0xffffffff, timer3_va_base + TIMER_LOAD);
|
|
writel(0xffffffff, timer3_va_base + TIMER_VALUE);
|
|
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
|
|
timer3_va_base + TIMER_CTRL);
|
|
|
|
clocksource_realview.mult =
|
|
clocksource_khz2mult(1000, clocksource_realview.shift);
|
|
clocksource_register(&clocksource_realview);
|
|
}
|
|
|
|
/*
|
|
* Set up the clock source and clock events devices
|
|
*/
|
|
void __init realview_timer_init(unsigned int timer_irq)
|
|
{
|
|
u32 val;
|
|
|
|
/*
|
|
* set clock frequency:
|
|
* REALVIEW_REFCLK is 32KHz
|
|
* REALVIEW_TIMCLK is 1MHz
|
|
*/
|
|
val = readl(__io_address(REALVIEW_SCTL_BASE));
|
|
writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
|
|
(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
|
|
(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
|
|
(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
|
|
__io_address(REALVIEW_SCTL_BASE));
|
|
|
|
/*
|
|
* Initialise to a known state (all timers off)
|
|
*/
|
|
writel(0, timer0_va_base + TIMER_CTRL);
|
|
writel(0, timer1_va_base + TIMER_CTRL);
|
|
writel(0, timer2_va_base + TIMER_CTRL);
|
|
writel(0, timer3_va_base + TIMER_CTRL);
|
|
|
|
/*
|
|
* Make irqs happen for the system timer
|
|
*/
|
|
setup_irq(timer_irq, &realview_timer_irq);
|
|
|
|
realview_clocksource_init();
|
|
realview_clockevents_init(timer_irq);
|
|
}
|
|
|
|
/*
|
|
* Setup the memory banks.
|
|
*/
|
|
void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
|
|
struct meminfo *meminfo)
|
|
{
|
|
/*
|
|
* Most RealView platforms have 512MB contiguous RAM at 0x70000000.
|
|
* Half of this is mirrored at 0.
|
|
*/
|
|
#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
|
|
meminfo->bank[0].start = 0x70000000;
|
|
meminfo->bank[0].size = SZ_512M;
|
|
meminfo->nr_banks = 1;
|
|
#else
|
|
meminfo->bank[0].start = 0;
|
|
meminfo->bank[0].size = SZ_256M;
|
|
meminfo->nr_banks = 1;
|
|
#endif
|
|
}
|