b31a1d8b41
Does the same for the accompanying MDIO driver, and then modifies the TBI configuration method. The old way used fields in einfo, which no longer exists. The new way is to create an MDIO device-tree node for each instance of gianfar, and create a tbi-handle property to associate ethernet controllers with the TBI PHYs they are connected to. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
341 lines
8.0 KiB
Plaintext
341 lines
8.0 KiB
Plaintext
/*
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* MPC8540 ADS Device Tree Source
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*
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* Copyright 2006, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "MPC8540ADS";
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compatible = "MPC8540ADS", "MPC85xxADS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8540@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // 166 MHz
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clock-frequency = <0>; // 825 MHz, from uboot
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x8000000>; // 128M at 0x0
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};
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soc8540@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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reg = <0xe0000000 0x100000>; // CCSRBAR 1M
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8540-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,8540-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8540-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <7 1>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x25520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x26520 0x20>;
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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};
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enet2: ethernet@26000 {
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cell-index = <2>;
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device_type = "network";
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model = "FEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <41 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi2>;
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phy-handle = <&phy3>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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pci0: pci@e0008000 {
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cell-index = <0>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x02 */
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0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x03 */
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0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x04 */
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0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
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0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
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0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
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0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x05 */
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0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x0c */
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0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x0d */
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0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x0e */
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0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
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0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
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0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
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0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x0f */
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0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
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0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
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0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
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/* IDSEL 0x12 */
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0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
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0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
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0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
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0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x13 */
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0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
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0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
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0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
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0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
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/* IDSEL 0x14 */
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0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
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0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
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0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
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0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
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/* IDSEL 0x15 */
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0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
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0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
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0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
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0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 0>;
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ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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};
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};
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