d87964c460
Move the GPIO suspend/resume support inline with the gpiolib support so that it will work with both the S3C24XX and S3C64XX series. The s3c_gpio_chip is extended to have a pm callback and a save block to keep the state of the GPIO over suspend, and the code from the s3c24xx implementation is added to a new common file. The suspend process now uses the list of registered chips to go through saving and restoring each one as appropriate, using the pm callback to select the appropriate routine depending on the type of control register present. This change also means that any additional GPIO added should not require changes to the PM. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
168 lines
3.5 KiB
C
168 lines
3.5 KiB
C
/* linux/arch/arm/plat-s3c24xx/gpiolib.c
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*
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* Copyright (c) 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <mach/gpio-core.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <plat/pm.h>
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#include <mach/regs-gpio.h>
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static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
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{
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return -EINVAL;
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}
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static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
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void __iomem *base = ourchip->base;
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unsigned long flags;
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unsigned long dat;
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unsigned long con;
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local_irq_save(flags);
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con = __raw_readl(base + 0x00);
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dat = __raw_readl(base + 0x04);
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dat &= ~(1 << offset);
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if (value)
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dat |= 1 << offset;
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__raw_writel(dat, base + 0x04);
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con &= ~(1 << offset);
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__raw_writel(con, base + 0x00);
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__raw_writel(dat, base + 0x04);
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local_irq_restore(flags);
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return 0;
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}
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static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
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{
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if (offset < 4)
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return IRQ_EINT0 + offset;
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if (offset < 8)
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return IRQ_EINT4 + offset - 4;
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return -EINVAL;
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}
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static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
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{
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return IRQ_EINT8 + offset;
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}
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struct s3c_gpio_chip s3c24xx_gpios[] = {
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[0] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
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.pm = __gpio_pm(&s3c_gpio_pm_1bit),
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.chip = {
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.base = S3C2410_GPA0,
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.owner = THIS_MODULE,
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.label = "GPIOA",
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.ngpio = 24,
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.direction_input = s3c24xx_gpiolib_banka_input,
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.direction_output = s3c24xx_gpiolib_banka_output,
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},
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},
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[1] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
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.pm = __gpio_pm(&s3c_gpio_pm_2bit),
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.chip = {
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.base = S3C2410_GPB0,
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.owner = THIS_MODULE,
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.label = "GPIOB",
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.ngpio = 16,
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},
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},
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[2] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
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.pm = __gpio_pm(&s3c_gpio_pm_2bit),
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.chip = {
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.base = S3C2410_GPC0,
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.owner = THIS_MODULE,
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.label = "GPIOC",
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.ngpio = 16,
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},
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},
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[3] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
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.pm = __gpio_pm(&s3c_gpio_pm_2bit),
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.chip = {
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.base = S3C2410_GPD0,
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.owner = THIS_MODULE,
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.label = "GPIOD",
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.ngpio = 16,
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},
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},
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[4] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
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.pm = __gpio_pm(&s3c_gpio_pm_2bit),
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.chip = {
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.base = S3C2410_GPE0,
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.label = "GPIOE",
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.owner = THIS_MODULE,
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.ngpio = 16,
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},
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},
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[5] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
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.pm = __gpio_pm(&s3c_gpio_pm_2bit),
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.chip = {
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.base = S3C2410_GPF0,
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.owner = THIS_MODULE,
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.label = "GPIOF",
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.ngpio = 8,
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.to_irq = s3c24xx_gpiolib_bankf_toirq,
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},
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},
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[6] = {
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.base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
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.pm = __gpio_pm(&s3c_gpio_pm_2bit),
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.chip = {
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.base = S3C2410_GPG0,
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.owner = THIS_MODULE,
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.label = "GPIOG",
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.ngpio = 10,
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.to_irq = s3c24xx_gpiolib_bankg_toirq,
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},
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},
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};
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static __init int s3c24xx_gpiolib_init(void)
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{
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struct s3c_gpio_chip *chip = s3c24xx_gpios;
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int gpn;
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for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
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s3c_gpiolib_add(chip);
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return 0;
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}
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arch_initcall(s3c24xx_gpiolib_init);
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