dbdf04c401
The Axon bridge chip used on new Cell/B.E. based blade servers comes with a DDR2 memory controller that can be used to attach cheap memory modules, as opposed to the high-speed XDR memory that is used by the CPU itself. Since the memory controller does not participate in the cache coherency protocol, we can not use the memory direcly for Linux applications, but by providing a block device it can be used for swap space, temporary file storage and through the use of the direct_access block device operation for mapping into user addresses, when it is mounted with an appropriate file system. Signed-off-by: Maxim Shchetynin <maxim@de.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
40 lines
1.2 KiB
Makefile
40 lines
1.2 KiB
Makefile
ifeq ($(CONFIG_PPC64),y)
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EXTRA_CFLAGS += -mno-minimal-toc
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endif
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mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o
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obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
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obj-$(CONFIG_PPC_MPC106) += grackle.o
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obj-$(CONFIG_PPC_DCR) += dcr.o
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obj-$(CONFIG_PPC_DCR_NATIVE) += dcr-low.o
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obj-$(CONFIG_PPC_PMI) += pmi.o
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obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
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mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
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obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o
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obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
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obj-$(CONFIG_AXON_RAM) += axonram.o
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# contains only the suspend handler for time
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ifeq ($(CONFIG_RTC_CLASS),)
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obj-$(CONFIG_PM) += timer.o
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endif
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ifeq ($(CONFIG_PPC_MERGE),y)
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obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
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obj-$(CONFIG_PPC_I8259) += i8259.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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obj-$(CONFIG_4xx) += uic.o
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endif
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# Temporary hack until we have migrated to asm-powerpc
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ifeq ($(ARCH),powerpc)
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obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
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obj-$(CONFIG_8xx) += mpc8xx_pic.o commproc.o
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obj-$(CONFIG_UCODE_PATCH) += micropatch.o
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endif
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