15f8c604a7
The way the current CPM binding describes available multi-user (a.k.a. dual-ported) RAM doesn't work well when there are multiple free regions, and it doesn't work at all if the region doesn't begin at the start of the muram area (as the hardware needs to be programmed with offsets into this area). The latter situation can happen with SMC UARTs on CPM2, as its parameter RAM is relocatable, u-boot puts it at zero, and the kernel doesn't support moving it. It is now described with a muram node, similar to QE. The current CPM binding is sufficiently recent (i.e. never appeared in an official release) that compatibility with existing device trees is not an issue. The code supporting the new binding is shared between cpm1 and cpm2, rather than remain separated. QE should be able to use this code as well, once minor fixes are made to its device trees. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
250 lines
5.9 KiB
Plaintext
250 lines
5.9 KiB
Plaintext
/*
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* MPC8272 ADS Device Tree Source
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*
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* Copyright 2005 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8272ADS";
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compatible = "fsl,mpc8272ads";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8272@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <d#32>;
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i-cache-line-size = <d#32>;
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d-cache-size = <d#16384>;
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i-cache-size = <d#16384>;
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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localbus@f0010100 {
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compatible = "fsl,mpc8272-localbus",
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"fsl,pq2-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <f0010100 40>;
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ranges = <0 0 fe000000 02000000
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1 0 f4500000 00008000
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3 0 f8200000 00008000>;
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flash@0,0 {
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compatible = "jedec-flash";
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reg = <0 0 2000000>;
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bank-width = <4>;
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device-width = <1>;
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};
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board-control@1,0 {
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reg = <1 0 20>;
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compatible = "fsl,mpc8272ads-bcsr";
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};
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PCI_PIC: interrupt-controller@3,0 {
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compatible = "fsl,mpc8272ads-pci-pic",
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"fsl,pq2ads-pci-pic";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <3 0 8>;
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interrupt-parent = <&PIC>;
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interrupts = <14 8>;
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};
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};
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pci@f0010800 {
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device_type = "pci";
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reg = <f0010800 10c f00101ac 8 f00101c4 8>;
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compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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clock-frequency = <d#66666666>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x16 */
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b000 0 0 1 &PCI_PIC 0
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b000 0 0 2 &PCI_PIC 1
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b000 0 0 3 &PCI_PIC 2
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b000 0 0 4 &PCI_PIC 3
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/* IDSEL 0x17 */
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b800 0 0 1 &PCI_PIC 4
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b800 0 0 2 &PCI_PIC 5
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b800 0 0 3 &PCI_PIC 6
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b800 0 0 4 &PCI_PIC 7
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/* IDSEL 0x18 */
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c000 0 0 1 &PCI_PIC 8
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c000 0 0 2 &PCI_PIC 9
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c000 0 0 3 &PCI_PIC a
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c000 0 0 4 &PCI_PIC b>;
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interrupt-parent = <&PIC>;
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interrupts = <12 8>;
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ranges = <42000000 0 80000000 80000000 0 20000000
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02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 f6000000 0 02000000>;
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};
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soc@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8272", "fsl,pq2-soc";
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ranges = <00000000 f0000000 00053000>;
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// Temporary -- will go away once kernel uses ranges for get_immrbase().
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reg = <f0000000 00053000>;
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cpm@119c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
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reg = <119c0 30 0 2000>;
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ranges;
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muram@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0 2000 9800 800>;
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};
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};
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brg@119f0 {
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compatible = "fsl,mpc8272-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <119f0 10 115f0 10>;
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};
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serial@11a00 {
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device_type = "serial";
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compatible = "fsl,mpc8272-scc-uart",
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"fsl,cpm2-scc-uart";
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reg = <11a00 20 8000 100>;
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interrupts = <28 8>;
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interrupt-parent = <&PIC>;
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fsl,cpm-brg = <1>;
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fsl,cpm-command = <00800000>;
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};
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serial@11a60 {
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device_type = "serial";
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compatible = "fsl,mpc8272-scc-uart",
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"fsl,cpm2-scc-uart";
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reg = <11a60 20 8300 100>;
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interrupts = <2b 8>;
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interrupt-parent = <&PIC>;
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fsl,cpm-brg = <4>;
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fsl,cpm-command = <0ce00000>;
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};
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mdio@10d40 {
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device_type = "mdio";
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compatible = "fsl,mpc8272ads-mdio-bitbang",
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"fsl,mpc8272-mdio-bitbang",
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"fsl,cpm2-mdio-bitbang";
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reg = <10d40 14>;
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#address-cells = <1>;
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#size-cells = <0>;
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fsl,mdio-pin = <12>;
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fsl,mdc-pin = <13>;
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PHY0: ethernet-phy@0 {
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interrupt-parent = <&PIC>;
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interrupts = <17 8>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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PHY1: ethernet-phy@1 {
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interrupt-parent = <&PIC>;
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interrupts = <17 8>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@11300 {
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device_type = "network";
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compatible = "fsl,mpc8272-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <11300 20 8400 100 11390 1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <20 8>;
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interrupt-parent = <&PIC>;
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phy-handle = <&PHY0>;
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linux,network-index = <0>;
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fsl,cpm-command = <12000300>;
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};
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ethernet@11320 {
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device_type = "network";
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compatible = "fsl,mpc8272-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <11320 20 8500 100 113b0 1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <21 8>;
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interrupt-parent = <&PIC>;
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phy-handle = <&PHY1>;
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linux,network-index = <1>;
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fsl,cpm-command = <16200300>;
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};
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};
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PIC: interrupt-controller@10c00 {
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <10c00 80>;
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compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
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};
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/* May need to remove if on a part without crypto engine */
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "fsl,mpc8272-talitos-sec2",
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"fsl,talitos-sec2",
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"fsl,talitos",
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"talitos";
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reg = <30000 10000>;
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interrupts = <b 8>;
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interrupt-parent = <&PIC>;
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num-channels = <4>;
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channel-fifo-len = <18>;
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exec-units-mask = <0000007e>;
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/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
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descriptor-types-mask = <01010ebf>;
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};
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};
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chosen {
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linux,stdout-path = "/soc/cpm/serial@11a00";
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};
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};
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