e481a52890
V3 of SCIF serial port support for the r8a73a4 SoC. This is done by adding platform devices for SCIFA0 -> SCIFA1 as well as SCIFB0 -> SCIFB3 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
94 lines
2.9 KiB
C
94 lines
2.9 KiB
C
/*
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* r8a73a4 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/serial_sci.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a73a4.h>
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#include <asm/mach/arch.h>
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#define SCIF_COMMON(scif_type, baseaddr, irq) \
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.type = scif_type, \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.irqs = SCIx_IRQ_MUXED(irq)
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#define SCIFA_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
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}
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#define SCIFB_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
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static const struct plat_sci_port scif[] = {
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SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
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SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
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SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
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SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
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SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
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SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
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};
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static inline void r8a73a4_register_scif(int idx)
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{
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platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
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sizeof(struct plat_sci_port));
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}
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void __init r8a73a4_add_standard_devices(void)
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{
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r8a73a4_register_scif(SCIFA0);
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r8a73a4_register_scif(SCIFA1);
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r8a73a4_register_scif(SCIFB0);
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r8a73a4_register_scif(SCIFB1);
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r8a73a4_register_scif(SCIFB2);
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r8a73a4_register_scif(SCIFB3);
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}
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#ifdef CONFIG_USE_OF
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void __init r8a73a4_add_standard_devices_dt(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char *r8a73a4_boards_compat_dt[] __initdata = {
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"renesas,r8a73a4",
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NULL,
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};
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DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
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.init_irq = irqchip_init,
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.init_machine = r8a73a4_add_standard_devices_dt,
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.init_time = shmobile_timer_init,
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.dt_compat = r8a73a4_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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