ebbb293f8b
The first version of the driver had hard-coded the logic for handling the checksum offloading. This was designed according to the chips included in the STM platforms where: o MAC10/100 supports no COE at all. o GMAC fully supports RX/TX COE. This is not good for other chip configurations where, for example, the mac10/100 supports the tx csum in HW or when the GMAC has no IPC. Thanks to Johannes Stezenbach; he provided me a first draft of this patch that only reviewed the IPC for the GMAC devices. This patch also helps on SPEAr platforms where the MAC10/100 can perform the TX csum in HW. Thanks to Deepak SIKRI for his support on this. In the end, GMAC devices for STM platforms have a bugged Jumbo frame support that needs to have the Tx COE disabled for oversized frames (due to limited buffer sizes). This information is also passed through the driver's platform structure. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Johannes Stezenbach <js@sig21.net> Signed-off-by: Deepak SIKRI <deepak.sikri@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
251 lines
7.3 KiB
C
251 lines
7.3 KiB
C
/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This only implements the mac core functions for this chip.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <linux/crc32.h>
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#include <linux/slab.h>
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#include "dwmac1000.h"
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static void dwmac1000_core_init(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + GMAC_CONTROL);
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value |= GMAC_CORE_INIT;
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writel(value, ioaddr + GMAC_CONTROL);
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/* STBus Bridge Configuration */
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/*writel(0xc5608, ioaddr + 0x00007000);*/
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/* Freeze MMC counters */
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writel(0x8, ioaddr + GMAC_MMC_CTRL);
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/* Mask GMAC interrupts */
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writel(0x207, ioaddr + GMAC_INT_MASK);
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#ifdef STMMAC_VLAN_TAG_USED
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/* Tag detection without filtering */
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writel(0x0, ioaddr + GMAC_VLAN_TAG);
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#endif
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}
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static int dwmac1000_rx_coe_supported(void __iomem *ioaddr)
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{
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u32 value = readl(ioaddr + GMAC_CONTROL);
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value |= GMAC_CONTROL_IPC;
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writel(value, ioaddr + GMAC_CONTROL);
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value = readl(ioaddr + GMAC_CONTROL);
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return !!(value & GMAC_CONTROL_IPC);
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}
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static void dwmac1000_dump_regs(void __iomem *ioaddr)
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{
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int i;
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pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
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for (i = 0; i < 55; i++) {
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int offset = i * 4;
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pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
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offset, readl(ioaddr + offset));
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}
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}
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static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
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unsigned int reg_n)
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{
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stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac1000_set_filter(struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *) dev->base_addr;
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unsigned int value = 0;
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CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
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__func__, netdev_mc_count(dev), netdev_uc_count(dev));
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if (dev->flags & IFF_PROMISC)
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value = GMAC_FRAME_FILTER_PR;
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else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
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|| (dev->flags & IFF_ALLMULTI)) {
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value = GMAC_FRAME_FILTER_PM; /* pass all multi */
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writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
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writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
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} else if (!netdev_mc_empty(dev)) {
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u32 mc_filter[2];
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struct netdev_hw_addr *ha;
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/* Hash filter for multicast */
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value = GMAC_FRAME_FILTER_HMC;
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memset(mc_filter, 0, sizeof(mc_filter));
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper 6 bits of the calculated CRC are used to
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index the contens of the hash table */
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int bit_nr =
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bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
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/* The most significant bit determines the register to
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* use (H/L) while the other 5 bits determine the bit
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* within the register. */
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mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
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}
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writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
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writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
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}
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/* Handle multiple unicast addresses (perfect filtering)*/
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if (netdev_uc_count(dev) > GMAC_MAX_UNICAST_ADDRESSES)
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/* Switch to promiscuous mode is more than 16 addrs
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are required */
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value |= GMAC_FRAME_FILTER_PR;
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else {
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int reg = 1;
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struct netdev_hw_addr *ha;
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netdev_for_each_uc_addr(ha, dev) {
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dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
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reg++;
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}
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}
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#ifdef FRAME_FILTER_DEBUG
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/* Enable Receive all mode (to debug filtering_fail errors) */
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value |= GMAC_FRAME_FILTER_RA;
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#endif
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writel(value, ioaddr + GMAC_FRAME_FILTER);
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CHIP_DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
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"HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
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readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
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}
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static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
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unsigned int fc, unsigned int pause_time)
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{
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unsigned int flow = 0;
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CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
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if (fc & FLOW_RX) {
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CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
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flow |= GMAC_FLOW_CTRL_RFE;
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}
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if (fc & FLOW_TX) {
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CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
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flow |= GMAC_FLOW_CTRL_TFE;
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}
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if (duplex) {
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CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
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flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
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}
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writel(flow, ioaddr + GMAC_FLOW_CTRL);
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}
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static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
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{
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unsigned int pmt = 0;
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if (mode == WAKE_MAGIC) {
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CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
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pmt |= power_down | magic_pkt_en;
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} else if (mode == WAKE_UCAST) {
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CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
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pmt |= global_unicast;
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}
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writel(pmt, ioaddr + GMAC_PMT);
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}
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static void dwmac1000_irq_status(void __iomem *ioaddr)
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{
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u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
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/* Not used events (e.g. MMC interrupts) are not handled. */
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if ((intr_status & mmc_tx_irq))
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CHIP_DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
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readl(ioaddr + GMAC_MMC_TX_INTR));
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if (unlikely(intr_status & mmc_rx_irq))
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CHIP_DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
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readl(ioaddr + GMAC_MMC_RX_INTR));
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if (unlikely(intr_status & mmc_rx_csum_offload_irq))
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CHIP_DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
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readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
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if (unlikely(intr_status & pmt_irq)) {
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CHIP_DBG(KERN_DEBUG "GMAC: received Magic frame\n");
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/* clear the PMT bits 5 and 6 by reading the PMT
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* status register. */
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readl(ioaddr + GMAC_PMT);
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}
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}
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struct stmmac_ops dwmac1000_ops = {
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.core_init = dwmac1000_core_init,
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.rx_coe = dwmac1000_rx_coe_supported,
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.dump_regs = dwmac1000_dump_regs,
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.host_irq_status = dwmac1000_irq_status,
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.set_filter = dwmac1000_set_filter,
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.flow_ctrl = dwmac1000_flow_ctrl,
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.pmt = dwmac1000_pmt,
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.set_umac_addr = dwmac1000_set_umac_addr,
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.get_umac_addr = dwmac1000_get_umac_addr,
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};
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struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
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{
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struct mac_device_info *mac;
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u32 uid = readl(ioaddr + GMAC_VERSION);
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pr_info("\tDWMAC1000 - user ID: 0x%x, Synopsys ID: 0x%x\n",
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((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
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mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
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if (!mac)
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return NULL;
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mac->mac = &dwmac1000_ops;
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mac->dma = &dwmac1000_dma_ops;
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mac->pmt = PMT_SUPPORTED;
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mac->link.port = GMAC_CONTROL_PS;
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mac->link.duplex = GMAC_CONTROL_DM;
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mac->link.speed = GMAC_CONTROL_FES;
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mac->mii.addr = GMAC_MII_ADDR;
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mac->mii.data = GMAC_MII_DATA;
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return mac;
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}
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