ee2d64f5cc
A major rewrite of interrupt handling for incoming mailbox processing, to split the timing critical steps from the the deferrable steps as the sending XPU on the CX23418 will time out and overwrite our incoming mailboxes rather quickly. Setup a pool of work "order forms" for the irq handler to send jobs to the new work handler routine which uses the kernel default work queue to do the deferrable work. Started optimizing some of the cx18-io calls as they are now the low hanging fruit for recoving microseconds back from the timeline. Future optimizations will get rid of mmio read retries, mmio stats logging, and combine smaller functions in the irq path into the larger ones to save ~2 us each. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
244 lines
6.0 KiB
C
244 lines
6.0 KiB
C
/*
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* cx18 driver PCI memory mapped IO access routines
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include "cx18-irq.h"
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void cx18_log_statistics(struct cx18 *cx)
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{
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int i;
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if (!(cx18_debug & CX18_DBGFLG_INFO))
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return;
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for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++)
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CX18_DEBUG_INFO("retried_write[%d] = %d\n", i,
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atomic_read(&cx->mmio_stats.retried_write[i]));
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for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++)
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CX18_DEBUG_INFO("retried_read[%d] = %d\n", i,
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atomic_read(&cx->mmio_stats.retried_read[i]));
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for (i = 0; i <= CX18_MAX_MB_ACK_DELAY; i++)
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if (atomic_read(&cx->mbox_stats.mb_ack_delay[i]))
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CX18_DEBUG_INFO("mb_ack_delay[%d] = %d\n", i,
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atomic_read(&cx->mbox_stats.mb_ack_delay[i]));
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return;
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}
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void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_raw_writel_noretry(cx, val, addr);
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if (val == cx18_raw_readl_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u32 val;
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for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_raw_readl_noretry(cx, addr);
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if (val != 0xffffffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u16 val;
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for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_raw_readw_noretry(cx, addr);
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if (val != 0xffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (val == cx18_readl_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
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u32 eval, u32 mask)
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{
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int i;
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eval &= mask;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writel_noretry(cx, val, addr);
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if (eval == (cx18_readl_noretry(cx, addr) & mask))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writew_noretry(cx, val, addr);
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if (val == cx18_readw_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr)
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{
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int i;
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for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
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cx18_writeb_noretry(cx, val, addr);
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if (val == cx18_readb_noretry(cx, addr))
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break;
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}
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cx18_log_write_retries(cx, i, addr);
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}
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u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u32 val;
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for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_readl_noretry(cx, addr);
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if (val != 0xffffffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u16 val;
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for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_readw_noretry(cx, addr);
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if (val != 0xffff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr)
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{
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int i;
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u8 val;
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for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) {
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val = cx18_readb_noretry(cx, addr);
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if (val != 0xff) /* PCI bus read error */
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break;
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}
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cx18_log_read_retries(cx, i, addr);
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return val;
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}
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void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
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{
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u8 __iomem *dst = addr;
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u16 val2 = val | (val << 8);
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u32 val4 = val2 | (val2 << 16);
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/* Align writes on the CX23418's addresses */
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if ((count > 0) && ((unsigned long)dst & 1)) {
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cx18_writeb(cx, (u8) val, dst);
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count--;
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dst++;
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}
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if ((count > 1) && ((unsigned long)dst & 2)) {
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cx18_writew(cx, val2, dst);
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count -= 2;
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dst += 2;
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}
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while (count > 3) {
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cx18_writel(cx, val4, dst);
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count -= 4;
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dst += 4;
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}
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if (count > 1) {
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cx18_writew(cx, val2, dst);
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count -= 2;
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dst += 2;
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}
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if (count > 0)
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cx18_writeb(cx, (u8) val, dst);
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}
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void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
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{
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u32 r;
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cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
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r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
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cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
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}
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void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
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{
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u32 r;
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r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
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cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
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{
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u32 r;
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cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
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r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
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cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
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{
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u32 r;
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r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
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cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI);
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}
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void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
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{
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u32 r;
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r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
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cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
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}
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void cx18_setup_page(struct cx18 *cx, u32 addr)
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{
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u32 val;
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val = cx18_read_reg(cx, 0xD000F8);
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val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
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cx18_write_reg(cx, val, 0xD000F8);
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}
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