eee45269b0
Thanks to Christoph for doing most of the work. This allows automatic SMP IRQ affinity assignment other than default "all interrupts on all CPUs" which is rather expensive. This might be useful if the hardware can be programmed to distribute interrupts among different CPUs, like Alpha does. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Christoph Hellwig <hch@lst.de> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
242 lines
6.0 KiB
C
242 lines
6.0 KiB
C
#ifndef __irq_h
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#define __irq_h
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/*
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* Please do not include this file in generic code. There is currently
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* no requirement for any architecture to implement anything held
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* within this file.
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*
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* Thanks. --rmk
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*/
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#include <linux/config.h>
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#include <linux/smp.h>
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#if !defined(CONFIG_ARCH_S390)
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#include <linux/linkage.h>
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#include <linux/cache.h>
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#include <linux/spinlock.h>
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#include <linux/cpumask.h>
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#include <asm/irq.h>
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#include <asm/ptrace.h>
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/*
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* IRQ line status.
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*/
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#define IRQ_INPROGRESS 1 /* IRQ handler active - do not enter! */
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#define IRQ_DISABLED 2 /* IRQ disabled - do not enter! */
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#define IRQ_PENDING 4 /* IRQ pending - replay on enable */
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#define IRQ_REPLAY 8 /* IRQ has been replayed but not acked yet */
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#define IRQ_AUTODETECT 16 /* IRQ is being autodetected */
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#define IRQ_WAITING 32 /* IRQ not yet seen - for autodetection */
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#define IRQ_LEVEL 64 /* IRQ level triggered */
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#define IRQ_MASKED 128 /* IRQ masked - shouldn't be seen again */
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#if defined(ARCH_HAS_IRQ_PER_CPU)
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# define IRQ_PER_CPU 256 /* IRQ is per CPU */
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# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
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#else
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# define CHECK_IRQ_PER_CPU(var) 0
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#endif
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/*
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* Interrupt controller descriptor. This is all we need
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* to describe about the low-level hardware.
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*/
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struct hw_interrupt_type {
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const char * typename;
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unsigned int (*startup)(unsigned int irq);
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void (*shutdown)(unsigned int irq);
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void (*enable)(unsigned int irq);
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void (*disable)(unsigned int irq);
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void (*ack)(unsigned int irq);
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void (*end)(unsigned int irq);
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void (*set_affinity)(unsigned int irq, cpumask_t dest);
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/* Currently used only by UML, might disappear one day.*/
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#ifdef CONFIG_IRQ_RELEASE_METHOD
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void (*release)(unsigned int irq, void *dev_id);
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#endif
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};
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typedef struct hw_interrupt_type hw_irq_controller;
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/*
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* This is the "IRQ descriptor", which contains various information
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* about the irq, including what kind of hardware handling it has,
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* whether it is disabled etc etc.
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*
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* Pad this out to 32 bytes for cache and indexing reasons.
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*/
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typedef struct irq_desc {
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hw_irq_controller *handler;
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void *handler_data;
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struct irqaction *action; /* IRQ action list */
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unsigned int status; /* IRQ status */
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unsigned int depth; /* nested irq disables */
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unsigned int irq_count; /* For detecting broken interrupts */
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unsigned int irqs_unhandled;
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spinlock_t lock;
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#if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE)
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unsigned int move_irq; /* Flag need to re-target intr dest*/
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#endif
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} ____cacheline_aligned irq_desc_t;
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extern irq_desc_t irq_desc [NR_IRQS];
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/* Return a pointer to the irq descriptor for IRQ. */
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static inline irq_desc_t *
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irq_descp (int irq)
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{
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return irq_desc + irq;
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}
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#include <asm/hw_irq.h> /* the arch dependent stuff */
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extern int setup_irq(unsigned int irq, struct irqaction * new);
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#ifdef CONFIG_GENERIC_HARDIRQS
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extern cpumask_t irq_affinity[NR_IRQS];
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#ifdef CONFIG_SMP
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static inline void set_native_irq_info(int irq, cpumask_t mask)
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{
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irq_affinity[irq] = mask;
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}
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#else
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static inline void set_native_irq_info(int irq, cpumask_t mask)
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{
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}
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#endif
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#ifdef CONFIG_SMP
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#if defined (CONFIG_GENERIC_PENDING_IRQ) || defined (CONFIG_IRQBALANCE)
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extern cpumask_t pending_irq_cpumask[NR_IRQS];
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static inline void set_pending_irq(unsigned int irq, cpumask_t mask)
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{
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irq_desc_t *desc = irq_desc + irq;
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unsigned long flags;
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spin_lock_irqsave(&desc->lock, flags);
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desc->move_irq = 1;
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pending_irq_cpumask[irq] = mask;
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spin_unlock_irqrestore(&desc->lock, flags);
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}
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static inline void
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move_native_irq(int irq)
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{
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cpumask_t tmp;
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irq_desc_t *desc = irq_descp(irq);
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if (likely (!desc->move_irq))
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return;
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desc->move_irq = 0;
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if (likely(cpus_empty(pending_irq_cpumask[irq])))
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return;
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if (!desc->handler->set_affinity)
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return;
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/* note - we hold the desc->lock */
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cpus_and(tmp, pending_irq_cpumask[irq], cpu_online_map);
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/*
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* If there was a valid mask to work with, please
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* do the disable, re-program, enable sequence.
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* This is *not* particularly important for level triggered
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* but in a edge trigger case, we might be setting rte
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* when an active trigger is comming in. This could
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* cause some ioapics to mal-function.
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* Being paranoid i guess!
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*/
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if (unlikely(!cpus_empty(tmp))) {
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desc->handler->disable(irq);
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desc->handler->set_affinity(irq,tmp);
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desc->handler->enable(irq);
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}
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cpus_clear(pending_irq_cpumask[irq]);
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}
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#ifdef CONFIG_PCI_MSI
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/*
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* Wonder why these are dummies?
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* For e.g the set_ioapic_affinity_vector() calls the set_ioapic_affinity_irq()
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* counter part after translating the vector to irq info. We need to perform
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* this operation on the real irq, when we dont use vector, i.e when
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* pci_use_vector() is false.
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*/
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static inline void move_irq(int irq)
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{
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}
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static inline void set_irq_info(int irq, cpumask_t mask)
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{
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}
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#else // CONFIG_PCI_MSI
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static inline void move_irq(int irq)
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{
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move_native_irq(irq);
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}
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static inline void set_irq_info(int irq, cpumask_t mask)
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{
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set_native_irq_info(irq, mask);
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}
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#endif // CONFIG_PCI_MSI
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#else // CONFIG_GENERIC_PENDING_IRQ || CONFIG_IRQBALANCE
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#define move_irq(x)
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#define move_native_irq(x)
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#define set_pending_irq(x,y)
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static inline void set_irq_info(int irq, cpumask_t mask)
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{
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set_native_irq_info(irq, mask);
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}
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#endif // CONFIG_GENERIC_PENDING_IRQ
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#else // CONFIG_SMP
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#define move_irq(x)
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#define move_native_irq(x)
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#endif // CONFIG_SMP
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extern int no_irq_affinity;
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extern int noirqdebug_setup(char *str);
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extern fastcall int handle_IRQ_event(unsigned int irq, struct pt_regs *regs,
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struct irqaction *action);
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extern fastcall unsigned int __do_IRQ(unsigned int irq, struct pt_regs *regs);
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extern void note_interrupt(unsigned int irq, irq_desc_t *desc,
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int action_ret, struct pt_regs *regs);
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extern int can_request_irq(unsigned int irq, unsigned long irqflags);
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extern void init_irq_proc(void);
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#ifdef CONFIG_AUTO_IRQ_AFFINITY
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extern int select_smp_affinity(unsigned int irq);
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#else
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static inline int
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select_smp_affinity(unsigned int irq)
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{
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return 1;
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}
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#endif
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#endif
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extern hw_irq_controller no_irq_type; /* needed in every arch ? */
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#endif
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#endif /* __irq_h */
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