59c348c38f
Add GPIO hwmod data for OMAP2420 and add the required GPIO device attributes in the gpio header file Also remove "omap24xx.h" header file as it is not required anymore. Signed-off-by: Charulatha V <charu@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
807 lines
21 KiB
C
807 lines
21 KiB
C
/*
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* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
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*
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* Copyright (C) 2009-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX handle crossbar/shared link difference for L3?
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* XXX these should be marked initdata for multi-OMAP kernels
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*/
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#include <plat/omap_hwmod.h>
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#include <mach/irqs.h>
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#include <plat/cpu.h>
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#include <plat/dma.h>
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#include <plat/serial.h>
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#include <plat/i2c.h>
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#include <plat/gpio.h>
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#include "omap_hwmod_common_data.h"
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#include "cm-regbits-24xx.h"
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#include "prm-regbits-24xx.h"
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/*
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* OMAP2420 hardware module integration data
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*
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* ALl of the data in this section should be autogeneratable from the
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* TI hardware database or other technical documentation. Data that
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* is driver-specific or driver-kernel integration-specific belongs
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* elsewhere.
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*/
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static struct omap_hwmod omap2420_mpu_hwmod;
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static struct omap_hwmod omap2420_iva_hwmod;
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static struct omap_hwmod omap2420_l3_main_hwmod;
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static struct omap_hwmod omap2420_l4_core_hwmod;
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static struct omap_hwmod omap2420_wd_timer2_hwmod;
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static struct omap_hwmod omap2420_gpio1_hwmod;
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static struct omap_hwmod omap2420_gpio2_hwmod;
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static struct omap_hwmod omap2420_gpio3_hwmod;
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static struct omap_hwmod omap2420_gpio4_hwmod;
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/* L3 -> L4_CORE interface */
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static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
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.master = &omap2420_l3_main_hwmod,
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.slave = &omap2420_l4_core_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* MPU -> L3 interface */
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static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
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.master = &omap2420_mpu_hwmod,
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.slave = &omap2420_l3_main_hwmod,
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.user = OCP_USER_MPU,
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};
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/* Slave interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
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&omap2420_mpu__l3_main,
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};
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/* Master interfaces on the L3 interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
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&omap2420_l3_main__l4_core,
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};
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/* L3 */
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static struct omap_hwmod omap2420_l3_main_hwmod = {
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.name = "l3_main",
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.class = &l3_hwmod_class,
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.masters = omap2420_l3_main_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
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.slaves = omap2420_l3_main_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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static struct omap_hwmod omap2420_l4_wkup_hwmod;
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static struct omap_hwmod omap2420_uart1_hwmod;
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static struct omap_hwmod omap2420_uart2_hwmod;
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static struct omap_hwmod omap2420_uart3_hwmod;
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static struct omap_hwmod omap2420_i2c1_hwmod;
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static struct omap_hwmod omap2420_i2c2_hwmod;
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/* L4_CORE -> L4_WKUP interface */
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static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_l4_wkup_hwmod,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART1 interface */
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static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
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{
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.pa_start = OMAP2_UART1_BASE,
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.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_uart1_hwmod,
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.clk = "uart1_ick",
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.addr = omap2420_uart1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> UART2 interface */
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static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
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{
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.pa_start = OMAP2_UART2_BASE,
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.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_uart2_hwmod,
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.clk = "uart2_ick",
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.addr = omap2420_uart2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 PER -> UART3 interface */
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static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
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{
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.pa_start = OMAP2_UART3_BASE,
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.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
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.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_uart3_hwmod,
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.clk = "uart3_ick",
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.addr = omap2420_uart3_addr_space,
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.addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* I2C IP block address space length (in bytes) */
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#define OMAP2_I2C_AS_LEN 128
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/* L4 CORE -> I2C1 interface */
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static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
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{
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.pa_start = 0x48070000,
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.pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_i2c1_hwmod,
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.clk = "i2c1_ick",
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.addr = omap2420_i2c1_addr_space,
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.addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* L4 CORE -> I2C2 interface */
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static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
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{
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.pa_start = 0x48072000,
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.pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
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.flags = ADDR_TYPE_RT,
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},
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};
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static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
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.master = &omap2420_l4_core_hwmod,
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.slave = &omap2420_i2c2_hwmod,
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.clk = "i2c2_ick",
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.addr = omap2420_i2c2_addr_space,
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.addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* Slave interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
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&omap2420_l3_main__l4_core,
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};
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/* Master interfaces on the L4_CORE interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
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&omap2420_l4_core__l4_wkup,
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&omap2_l4_core__uart1,
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&omap2_l4_core__uart2,
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&omap2_l4_core__uart3,
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&omap2420_l4_core__i2c1,
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&omap2420_l4_core__i2c2
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};
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/* L4 CORE */
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static struct omap_hwmod omap2420_l4_core_hwmod = {
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.name = "l4_core",
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.class = &l4_hwmod_class,
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.masters = omap2420_l4_core_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
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.slaves = omap2420_l4_core_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Slave interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
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&omap2420_l4_core__l4_wkup,
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};
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/* Master interfaces on the L4_WKUP interconnect */
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static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
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};
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/* L4 WKUP */
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static struct omap_hwmod omap2420_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &l4_hwmod_class,
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.masters = omap2420_l4_wkup_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
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.slaves = omap2420_l4_wkup_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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.flags = HWMOD_NO_IDLEST,
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};
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/* Master interfaces on the MPU device */
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static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
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&omap2420_mpu__l3_main,
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};
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/* MPU */
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static struct omap_hwmod omap2420_mpu_hwmod = {
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.name = "mpu",
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.class = &mpu_hwmod_class,
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.main_clk = "mpu_ck",
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.masters = omap2420_mpu_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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/*
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* IVA1 interface data
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*/
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/* IVA <- L3 interface */
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static struct omap_hwmod_ocp_if omap2420_l3__iva = {
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.master = &omap2420_l3_main_hwmod,
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.slave = &omap2420_iva_hwmod,
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.clk = "iva1_ifck",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
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&omap2420_l3__iva,
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};
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/*
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* IVA2 (IVA2)
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*/
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static struct omap_hwmod omap2420_iva_hwmod = {
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.name = "iva",
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.class = &iva_hwmod_class,
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.masters = omap2420_iva_masters,
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.masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
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};
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/* l4_wkup -> wd_timer2 */
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static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
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{
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.pa_start = 0x48022000,
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.pa_end = 0x4802207f,
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.flags = ADDR_TYPE_RT
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},
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};
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static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
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.master = &omap2420_l4_wkup_hwmod,
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.slave = &omap2420_wd_timer2_hwmod,
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.clk = "mpu_wdt_ick",
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.addr = omap2420_wd_timer2_addrs,
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.addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/*
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* 'wd_timer' class
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* 32-bit watchdog upward counter that generates a pulse on the reset pin on
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* overflow condition
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*/
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static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
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.name = "wd_timer",
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.sysc = &omap2420_wd_timer_sysc,
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};
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/* wd_timer2 */
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static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
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&omap2420_l4_wkup__wd_timer2,
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};
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static struct omap_hwmod omap2420_wd_timer2_hwmod = {
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.name = "wd_timer2",
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.class = &omap2420_wd_timer_hwmod_class,
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.main_clk = "mpu_wdt_fck",
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.prcm = {
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.omap2 = {
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
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.module_offs = WKUP_MOD,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
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},
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},
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.slaves = omap2420_wd_timer2_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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/* UART */
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static struct omap_hwmod_class_sysconfig uart_sysc = {
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.rev_offs = 0x50,
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.sysc_offs = 0x54,
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.syss_offs = 0x58,
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.sysc_flags = (SYSC_HAS_SIDLEMODE |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class uart_class = {
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.name = "uart",
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.sysc = &uart_sysc,
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};
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/* UART1 */
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static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
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{ .irq = INT_24XX_UART1_IRQ, },
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};
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static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
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};
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static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
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&omap2_l4_core__uart1,
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};
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static struct omap_hwmod omap2420_uart1_hwmod = {
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.name = "uart1",
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.mpu_irqs = uart1_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
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.sdma_reqs = uart1_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
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.main_clk = "uart1_fck",
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.prcm = {
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.omap2 = {
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.module_offs = CORE_MOD,
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.prcm_reg_id = 1,
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.module_bit = OMAP24XX_EN_UART1_SHIFT,
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.idlest_reg_id = 1,
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.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
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},
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},
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.slaves = omap2420_uart1_slaves,
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.slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
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.class = &uart_class,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
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};
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/* UART2 */
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static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
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{ .irq = INT_24XX_UART2_IRQ, },
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};
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static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
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};
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static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
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&omap2_l4_core__uart2,
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};
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static struct omap_hwmod omap2420_uart2_hwmod = {
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.name = "uart2",
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.mpu_irqs = uart2_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
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.sdma_reqs = uart2_sdma_reqs,
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.sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
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.main_clk = "uart2_fck",
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.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP24XX_EN_UART2_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_uart2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
/* UART3 */
|
|
|
|
static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_UART3_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
|
|
&omap2_l4_core__uart3,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_uart3_hwmod = {
|
|
.name = "uart3",
|
|
.mpu_irqs = uart3_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
|
|
.sdma_reqs = uart3_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
|
|
.main_clk = "uart3_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 2,
|
|
.module_bit = OMAP24XX_EN_UART3_SHIFT,
|
|
.idlest_reg_id = 2,
|
|
.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_uart3_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
|
|
.class = &uart_class,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
/* I2C common */
|
|
static struct omap_hwmod_class_sysconfig i2c_sysc = {
|
|
.rev_offs = 0x00,
|
|
.sysc_offs = 0x20,
|
|
.syss_offs = 0x10,
|
|
.sysc_flags = SYSC_HAS_SOFTRESET,
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class i2c_class = {
|
|
.name = "i2c",
|
|
.sysc = &i2c_sysc,
|
|
};
|
|
|
|
static struct omap_i2c_dev_attr i2c_dev_attr;
|
|
|
|
/* I2C1 */
|
|
|
|
static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_I2C1_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
|
|
&omap2420_l4_core__i2c1,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_i2c1_hwmod = {
|
|
.name = "i2c1",
|
|
.mpu_irqs = i2c1_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
|
|
.sdma_reqs = i2c1_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
|
|
.main_clk = "i2c1_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP2420_EN_I2C1_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_i2c1_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
|
|
.class = &i2c_class,
|
|
.dev_attr = &i2c_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
.flags = HWMOD_16BIT_REG,
|
|
};
|
|
|
|
/* I2C2 */
|
|
|
|
static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
|
|
{ .irq = INT_24XX_I2C2_IRQ, },
|
|
};
|
|
|
|
static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
|
|
&omap2420_l4_core__i2c2,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_i2c2_hwmod = {
|
|
.name = "i2c2",
|
|
.mpu_irqs = i2c2_mpu_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
|
|
.sdma_reqs = i2c2_sdma_reqs,
|
|
.sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
|
|
.main_clk = "i2c2_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.module_offs = CORE_MOD,
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP2420_EN_I2C2_SHIFT,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_i2c2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
|
|
.class = &i2c_class,
|
|
.dev_attr = &i2c_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
.flags = HWMOD_16BIT_REG,
|
|
};
|
|
|
|
/* l4_wkup -> gpio1 */
|
|
static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
|
|
{
|
|
.pa_start = 0x48018000,
|
|
.pa_end = 0x480181ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
|
|
.master = &omap2420_l4_wkup_hwmod,
|
|
.slave = &omap2420_gpio1_hwmod,
|
|
.clk = "gpios_ick",
|
|
.addr = omap2420_gpio1_addr_space,
|
|
.addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio2 */
|
|
static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
|
|
{
|
|
.pa_start = 0x4801a000,
|
|
.pa_end = 0x4801a1ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
|
|
.master = &omap2420_l4_wkup_hwmod,
|
|
.slave = &omap2420_gpio2_hwmod,
|
|
.clk = "gpios_ick",
|
|
.addr = omap2420_gpio2_addr_space,
|
|
.addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio3 */
|
|
static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
|
|
{
|
|
.pa_start = 0x4801c000,
|
|
.pa_end = 0x4801c1ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
|
|
.master = &omap2420_l4_wkup_hwmod,
|
|
.slave = &omap2420_gpio3_hwmod,
|
|
.clk = "gpios_ick",
|
|
.addr = omap2420_gpio3_addr_space,
|
|
.addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> gpio4 */
|
|
static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
|
|
{
|
|
.pa_start = 0x4801e000,
|
|
.pa_end = 0x4801e1ff,
|
|
.flags = ADDR_TYPE_RT
|
|
},
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
|
|
.master = &omap2420_l4_wkup_hwmod,
|
|
.slave = &omap2420_gpio4_hwmod,
|
|
.clk = "gpios_ick",
|
|
.addr = omap2420_gpio4_addr_space,
|
|
.addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* gpio dev_attr */
|
|
static struct omap_gpio_dev_attr gpio_dev_attr = {
|
|
.bank_width = 32,
|
|
.dbck_flag = false,
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
/*
|
|
* 'gpio' class
|
|
* general purpose io module
|
|
*/
|
|
static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
|
|
.name = "gpio",
|
|
.sysc = &omap242x_gpio_sysc,
|
|
.rev = 0,
|
|
};
|
|
|
|
/* gpio1 */
|
|
static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
|
|
{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
|
|
&omap2420_l4_wkup__gpio1,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_gpio1_hwmod = {
|
|
.name = "gpio1",
|
|
.mpu_irqs = omap242x_gpio1_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
|
|
.main_clk = "gpios_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_gpio1_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
|
|
.class = &omap242x_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
/* gpio2 */
|
|
static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
|
|
{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
|
|
&omap2420_l4_wkup__gpio2,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_gpio2_hwmod = {
|
|
.name = "gpio2",
|
|
.mpu_irqs = omap242x_gpio2_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
|
|
.main_clk = "gpios_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_gpio2_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
|
|
.class = &omap242x_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
/* gpio3 */
|
|
static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
|
|
{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
|
|
&omap2420_l4_wkup__gpio3,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_gpio3_hwmod = {
|
|
.name = "gpio3",
|
|
.mpu_irqs = omap242x_gpio3_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
|
|
.main_clk = "gpios_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_gpio3_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
|
|
.class = &omap242x_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
/* gpio4 */
|
|
static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
|
|
{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
|
|
&omap2420_l4_wkup__gpio4,
|
|
};
|
|
|
|
static struct omap_hwmod omap2420_gpio4_hwmod = {
|
|
.name = "gpio4",
|
|
.mpu_irqs = omap242x_gpio4_irqs,
|
|
.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
|
|
.main_clk = "gpios_fck",
|
|
.prcm = {
|
|
.omap2 = {
|
|
.prcm_reg_id = 1,
|
|
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
|
.module_offs = WKUP_MOD,
|
|
.idlest_reg_id = 1,
|
|
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
|
},
|
|
},
|
|
.slaves = omap2420_gpio4_slaves,
|
|
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
|
|
.class = &omap242x_gpio_hwmod_class,
|
|
.dev_attr = &gpio_dev_attr,
|
|
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
|
};
|
|
|
|
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
|
|
&omap2420_l3_main_hwmod,
|
|
&omap2420_l4_core_hwmod,
|
|
&omap2420_l4_wkup_hwmod,
|
|
&omap2420_mpu_hwmod,
|
|
&omap2420_iva_hwmod,
|
|
&omap2420_wd_timer2_hwmod,
|
|
&omap2420_uart1_hwmod,
|
|
&omap2420_uart2_hwmod,
|
|
&omap2420_uart3_hwmod,
|
|
&omap2420_i2c1_hwmod,
|
|
&omap2420_i2c2_hwmod,
|
|
|
|
/* gpio class */
|
|
&omap2420_gpio1_hwmod,
|
|
&omap2420_gpio2_hwmod,
|
|
&omap2420_gpio3_hwmod,
|
|
&omap2420_gpio4_hwmod,
|
|
NULL,
|
|
};
|
|
|
|
int __init omap2420_hwmod_init(void)
|
|
{
|
|
return omap_hwmod_init(omap2420_hwmods);
|
|
}
|