f630c1bdfb
This patch implements a workaround for erratum 764369 affecting Cortex-A9 MPCore with two or more processors (all current revisions). Under certain timing circumstances, a data cache line maintenance operation by MVA targeting an Inner Shareable memory region may fail to proceed up to either the Point of Coherency or to the Point of Unification of the system. This workaround adds a DSB instruction before the relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. Cc: <stable@kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
88 lines
2.0 KiB
C
88 lines
2.0 KiB
C
/*
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* linux/arch/arm/kernel/smp_scu.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/smp_scu.h>
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#include <asm/cacheflush.h>
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#include <asm/cputype.h>
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#define SCU_CTRL 0x00
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#define SCU_CONFIG 0x04
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#define SCU_CPU_STATUS 0x08
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#define SCU_INVALIDATE 0x0c
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#define SCU_FPGA_REVISION 0x10
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#ifdef CONFIG_SMP
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/*
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* Get the number of CPU cores from the SCU configuration
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*/
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unsigned int __init scu_get_core_count(void __iomem *scu_base)
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{
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unsigned int ncores = __raw_readl(scu_base + SCU_CONFIG);
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return (ncores & 0x03) + 1;
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}
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/*
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* Enable the SCU
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*/
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void __init scu_enable(void __iomem *scu_base)
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{
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u32 scu_ctrl;
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#ifdef CONFIG_ARM_ERRATA_764369
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/* Cortex-A9 only */
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if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
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scu_ctrl = __raw_readl(scu_base + 0x30);
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if (!(scu_ctrl & 1))
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__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
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}
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#endif
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scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
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/* already enabled? */
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if (scu_ctrl & 1)
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return;
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scu_ctrl |= 1;
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__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
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/*
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* Ensure that the data accessed by CPU0 before the SCU was
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* initialised is visible to the other CPUs.
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*/
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flush_cache_all();
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}
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#endif
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/*
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* Set the executing CPUs power mode as defined. This will be in
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* preparation for it executing a WFI instruction.
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*
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* This function must be called with preemption disabled, and as it
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* has the side effect of disabling coherency, caches must have been
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* flushed. Interrupts must also have been disabled.
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*/
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int scu_power_mode(void __iomem *scu_base, unsigned int mode)
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{
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unsigned int val;
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int cpu = smp_processor_id();
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if (mode > 3 || mode == 1 || cpu > 3)
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return -EINVAL;
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val = __raw_readb(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;
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val |= mode;
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__raw_writeb(val, scu_base + SCU_CPU_STATUS + cpu);
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return 0;
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}
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