078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
163 lines
4.1 KiB
C
163 lines
4.1 KiB
C
/*
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* Malta Platform-specific hooks for SMP operation
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*/
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#include <linux/irq.h>
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#include <linux/init.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/smtc.h>
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#include <asm/smtc_ipi.h>
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/* VPE/SMP Prototype implements platform interfaces directly */
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/*
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* Cause the specified action to be performed on a targeted "CPU"
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*/
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static void msmtc_send_ipi_single(int cpu, unsigned int action)
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{
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/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
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smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
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}
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static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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{
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unsigned int i;
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for_each_cpu(i, mask)
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msmtc_send_ipi_single(i, action);
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}
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/*
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* Post-config but pre-boot cleanup entry point
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*/
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static void msmtc_init_secondary(void)
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{
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int myvpe;
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/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
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myvpe = read_c0_tcbind() & TCBIND_CURVPE;
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if (myvpe != 0) {
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/* Ideally, this should be done only once per VPE, but... */
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clear_c0_status(ST0_IM);
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set_c0_status((0x100 << cp0_compare_irq)
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| (0x100 << MIPS_CPU_IPI_IRQ));
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if (cp0_perfcount_irq >= 0)
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set_c0_status(0x100 << cp0_perfcount_irq);
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}
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smtc_init_secondary();
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}
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/*
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* Platform "CPU" startup hook
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*/
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static void msmtc_boot_secondary(int cpu, struct task_struct *idle)
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{
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smtc_boot_secondary(cpu, idle);
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}
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/*
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* SMP initialization finalization entry point
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*/
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static void msmtc_smp_finish(void)
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{
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smtc_smp_finish();
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}
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/*
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* Hook for after all CPUs are online
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*/
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static void msmtc_cpus_done(void)
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{
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}
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/*
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* Platform SMP pre-initialization
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*
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* As noted above, we can assume a single CPU for now
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* but it may be multithreaded.
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*/
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static void __init msmtc_smp_setup(void)
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{
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/*
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* we won't get the definitive value until
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* we've run smtc_prepare_cpus later, but
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* we would appear to need an upper bound now.
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*/
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smp_num_siblings = smtc_build_cpu_map(0);
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}
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static void __init msmtc_prepare_cpus(unsigned int max_cpus)
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{
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smtc_prepare_cpus(max_cpus);
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}
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struct plat_smp_ops msmtc_smp_ops = {
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.send_ipi_single = msmtc_send_ipi_single,
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.send_ipi_mask = msmtc_send_ipi_mask,
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.init_secondary = msmtc_init_secondary,
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.smp_finish = msmtc_smp_finish,
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.cpus_done = msmtc_cpus_done,
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.boot_secondary = msmtc_boot_secondary,
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.smp_setup = msmtc_smp_setup,
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.prepare_cpus = msmtc_prepare_cpus,
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};
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#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
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/*
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* IRQ affinity hook
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*/
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int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
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bool force)
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{
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cpumask_t tmask;
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int cpu = 0;
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void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff);
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/*
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* On the legacy Malta development board, all I/O interrupts
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* are routed through the 8259 and combined in a single signal
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* to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
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* that signal is brought to IP2 of both VPEs. To avoid racing
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* concurrent interrupt service events, IP2 is enabled only on
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* one VPE, by convention VPE0. So long as no bits are ever
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* cleared in the affinity mask, there will never be any
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* interrupt forwarding. But as soon as a program or operator
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* sets affinity for one of the related IRQs, we need to make
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* sure that we don't ever try to forward across the VPE boundary,
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* at least not until we engineer a system where the interrupt
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* _ack() or _end() function can somehow know that it corresponds
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* to an interrupt taken on another VPE, and perform the appropriate
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* restoration of Status.IM state using MFTR/MTTR instead of the
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* normal local behavior. We also ensure that no attempt will
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* be made to forward to an offline "CPU".
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*/
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cpumask_copy(&tmask, affinity);
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for_each_cpu(cpu, affinity) {
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if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
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cpu_clear(cpu, tmask);
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}
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cpumask_copy(d->affinity, &tmask);
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if (cpus_empty(tmask))
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/*
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* We could restore a default mask here, but the
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* runtime code can anyway deal with the null set
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*/
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printk(KERN_WARNING
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"IRQ affinity leaves no legal CPU for IRQ %d\n", d->irq);
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/* Do any generic SMTC IRQ affinity setup */
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smtc_set_irq_affinity(d->irq, tmask);
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
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