b89cd71a15
The AXI protocol specifies that the write response can only be sent back to an AXI master when the last write data has been accepted. This optimization enables the PL310 to send the write response of certain write transactions as soon as the store buffer accepts the write address. This behavior is not compatible with the AXI protocol and is disabled by default. You enable this optimization by setting the Early BRESP Enable bit in the Auxiliary Control Register (bit [30]). Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mans Rullgard <mans@mansr.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
106 lines
2.5 KiB
C
106 lines
2.5 KiB
C
/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/hardware.h>
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#include <mach/omap4-common.h>
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2cache_base;
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#endif
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void __iomem *gic_cpu_base_addr;
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void __iomem *gic_dist_base_addr;
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void __init gic_init_irq(void)
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{
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/* Static mapping, never released */
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gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
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BUG_ON(!gic_dist_base_addr);
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gic_dist_init(0, gic_dist_base_addr, 29);
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/* Static mapping, never released */
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gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
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BUG_ON(!gic_cpu_base_addr);
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gic_cpu_init(0, gic_cpu_base_addr);
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}
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#ifdef CONFIG_CACHE_L2X0
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static void omap4_l2x0_disable(void)
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{
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/* Disable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x0);
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}
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static int __init omap_l2_cache_init(void)
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{
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u32 aux_ctrl = 0;
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (!cpu_is_omap44xx())
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return -ENODEV;
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/* Static mapping, never released */
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l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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BUG_ON(!l2cache_base);
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/*
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* 16-way associativity, parity disabled
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* Way size - 32KB (es1.0)
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* Way size - 64KB (es2.0 +)
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*/
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aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
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(0x1 << 25) |
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(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
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(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
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} else {
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aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
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(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
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(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
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(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
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}
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if (omap_rev() != OMAP4430_REV_ES1_0)
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omap_smc1(0x109, aux_ctrl);
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/* Enable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x1);
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l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
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/*
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* Override default outer_cache.disable with a OMAP4
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* specific one
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*/
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outer_cache.disable = omap4_l2x0_disable;
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return 0;
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}
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early_initcall(omap_l2_cache_init);
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#endif
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