02c981c07b
SiRFprimaII is the latest generation application processor from CSR’s Multifunction SoC product family. Designed around an ARM cortex A9 core, high-speed memory bus, advanced 3D accelerator and full-HD multi-format video decoder, SiRFprimaII is able to meet the needs of complicated applications for modern multifunction devices that require heavy concurrent applications and fluid user experience. Integrated with GPS baseband, analog and PMU, this new platform is designed to provide a cost effective solution for Automotive and Consumer markets. This patch adds the basic support for this SoC and EVB board based on device tree. It is following the ZYNQ of Xilinx in some degree. Signed-off-by: Binghua Duan <Binghua.Duan@csr.com> Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com> Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Huayi Li <Huayi.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
24 lines
634 B
C
24 lines
634 B
C
/*
|
|
* arch/arm/mach-prima2/include/mach/uart.h
|
|
*
|
|
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
|
*
|
|
* Licensed under GPLv2 or later.
|
|
*/
|
|
|
|
#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
|
|
#define __MACH_PRIMA2_SIRFSOC_UART_H
|
|
|
|
/* UART-1: used as serial debug port */
|
|
#define SIRFSOC_UART1_PA_BASE 0xb0060000
|
|
#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
|
|
#define SIRFSOC_UART1_SIZE SZ_4K
|
|
|
|
#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
|
|
#define SIRFSOC_UART_TXFIFO_DATA 0x0118
|
|
|
|
#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
|
|
#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
|
|
|
|
#endif
|