c7d24a2dd0
Update the MPC8610 HPCD files to support the audio driver. Update booting-without-of.txt with information on the SSI device. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
313 lines
7.4 KiB
Plaintext
313 lines
7.4 KiB
Plaintext
/*
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* MPC8610 HPCD Device Tree Source
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*
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* Copyright 2007-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License Version 2 as published
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* by the Free Software Foundation.
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*/
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/ {
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model = "MPC8610HPCD";
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compatible = "fsl,MPC8610HPCD";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8610@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <d# 32>; // bytes
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i-cache-line-size = <d# 32>; // bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 20000000>; // 512M at 0x0
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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compatible = "fsl,mpc8610-immr", "simple-bus";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 1000>;
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bus-frequency = <0>;
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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cs4270:codec@4f {
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compatible = "cirrus,cs4270";
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reg = <4f>;
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/* MCLK source is a stand-alone oscillator */
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clock-frequency = <bb8000>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <3100 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <1c 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: interrupt-controller@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8610-guts";
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reg = <e0000 1000>;
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fsl,has-rstcr;
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};
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i2s@16000 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <0>;
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reg = <16000 100>;
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interrupt-parent = <&mpic>;
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interrupts = <3e 2>;
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fsl,mode = "i2s-slave";
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codec-handle = <&cs4270>;
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};
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ssi@16100 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <1>;
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reg = <16100 100>;
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interrupt-parent = <&mpic>;
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interrupts = <3f 2>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
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cell-index = <0>;
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reg = <21300 4>; /* DMA general status register */
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ranges = <0 21100 200>;
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dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <0>;
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reg = <0 80>;
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interrupt-parent = <&mpic>;
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interrupts = <14 2>;
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};
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dma-channel@1 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <1>;
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reg = <80 80>;
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interrupt-parent = <&mpic>;
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interrupts = <15 2>;
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};
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dma-channel@2 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <2>;
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reg = <100 80>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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dma-channel@3 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <3>;
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reg = <180 80>;
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interrupt-parent = <&mpic>;
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interrupts = <17 2>;
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};
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
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cell-index = <1>;
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reg = <c300 4>; /* DMA general status register */
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ranges = <0 c100 200>;
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dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <0>;
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reg = <0 80>;
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interrupt-parent = <&mpic>;
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interrupts = <3c 2>;
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};
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dma-channel@1 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <1>;
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reg = <80 80>;
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interrupt-parent = <&mpic>;
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interrupts = <3d 2>;
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};
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dma-channel@2 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <2>;
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reg = <100 80>;
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interrupt-parent = <&mpic>;
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interrupts = <3e 2>;
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};
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dma-channel@3 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,mpc8540-dma-channel";
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cell-index = <3>;
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reg = <180 80>;
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interrupt-parent = <&mpic>;
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interrupts = <3f 2>;
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};
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};
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};
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pci0: pci@e0008000 {
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cell-index = <0>;
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compatible = "fsl,mpc8610-pci";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008000 1000>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 e1000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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8800 0 0 1 &mpic 4 1
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8800 0 0 2 &mpic 5 1
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8800 0 0 3 &mpic 6 1
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8800 0 0 4 &mpic 7 1
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/* IDSEL 0x12 */
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9000 0 0 1 &mpic 5 1
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9000 0 0 2 &mpic 6 1
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9000 0 0 3 &mpic 7 1
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9000 0 0 4 &mpic 4 1
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>;
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};
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pci1: pcie@e000a000 {
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cell-index = <1>;
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e000a000 1000>;
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bus-range = <1 3>;
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ranges = <02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 e3000000 0 00100000>;
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clock-frequency = <1fca055>;
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interrupt-parent = <&mpic>;
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interrupts = <1a 2>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x1b */
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d800 0 0 1 &mpic 2 1
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/* IDSEL 0x1c*/
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e000 0 0 1 &mpic 1 1
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e000 0 0 2 &mpic 1 1
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e000 0 0 3 &mpic 1 1
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e000 0 0 4 &mpic 1 1
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/* IDSEL 0x1f */
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f800 0 0 1 &mpic 3 0
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f800 0 0 2 &mpic 0 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <02000000 0 a0000000
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02000000 0 a0000000
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0 10000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 a0000000
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02000000 0 a0000000
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0 10000000
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01000000 0 00000000
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01000000 0 00000000
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0 00100000>;
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};
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};
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};
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};
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