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@@ -577,6 +577,65 @@ static void xhci_restore_registers(struct xhci_hcd *xhci)
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xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
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}
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static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
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{
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u64 val_64;
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/* step 2: initialize command ring buffer */
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val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
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(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
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xhci->cmd_ring->dequeue) &
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(u64) ~CMD_RING_RSVD_BITS) |
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xhci->cmd_ring->cycle_state;
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xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
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(long unsigned long) val_64);
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xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
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}
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/*
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* The whole command ring must be cleared to zero when we suspend the host.
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*
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* The host doesn't save the command ring pointer in the suspend well, so we
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* need to re-program it on resume. Unfortunately, the pointer must be 64-byte
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* aligned, because of the reserved bits in the command ring dequeue pointer
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* register. Therefore, we can't just set the dequeue pointer back in the
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* middle of the ring (TRBs are 16-byte aligned).
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*/
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static void xhci_clear_command_ring(struct xhci_hcd *xhci)
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{
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struct xhci_ring *ring;
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struct xhci_segment *seg;
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ring = xhci->cmd_ring;
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seg = ring->deq_seg;
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do {
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memset(seg->trbs, 0, SEGMENT_SIZE);
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seg = seg->next;
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} while (seg != ring->deq_seg);
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/* Reset the software enqueue and dequeue pointers */
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ring->deq_seg = ring->first_seg;
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ring->dequeue = ring->first_seg->trbs;
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ring->enq_seg = ring->deq_seg;
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ring->enqueue = ring->dequeue;
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/*
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* Ring is now zeroed, so the HW should look for change of ownership
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* when the cycle bit is set to 1.
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*/
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ring->cycle_state = 1;
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/*
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* Reset the hardware dequeue pointer.
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* Yes, this will need to be re-written after resume, but we're paranoid
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* and want to make sure the hardware doesn't access bogus memory
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* because, say, the BIOS or an SMI started the host without changing
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* the command ring pointers.
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*/
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xhci_set_cmd_ring_deq(xhci);
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}
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/*
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* Stop HC (not bus-specific)
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*
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@@ -604,6 +663,7 @@ int xhci_suspend(struct xhci_hcd *xhci)
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spin_unlock_irq(&xhci->lock);
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return -ETIMEDOUT;
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}
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xhci_clear_command_ring(xhci);
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/* step 3: save registers */
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xhci_save_registers(xhci);
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@@ -635,7 +695,6 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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u32 command, temp = 0;
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struct usb_hcd *hcd = xhci_to_hcd(xhci);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u64 val_64;
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int old_state, retval;
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old_state = hcd->state;
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@@ -648,15 +707,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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/* step 1: restore register */
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xhci_restore_registers(xhci);
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/* step 2: initialize command ring buffer */
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val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
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(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
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xhci->cmd_ring->dequeue) &
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(u64) ~CMD_RING_RSVD_BITS) |
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xhci->cmd_ring->cycle_state;
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xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
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(long unsigned long) val_64);
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xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
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xhci_set_cmd_ring_deq(xhci);
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/* step 3: restore state and start state*/
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/* step 3: set CRS flag */
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command = xhci_readl(xhci, &xhci->op_regs->command);
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@@ -714,6 +765,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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return retval;
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}
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spin_unlock_irq(&xhci->lock);
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/* Re-setup MSI-X */
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if (hcd->irq)
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free_irq(hcd->irq, hcd);
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@@ -736,6 +788,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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hcd->irq = pdev->irq;
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}
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spin_lock_irq(&xhci->lock);
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/* step 4: set Run/Stop bit */
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command |= CMD_RUN;
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