x86, mtrr: replace MTRRdefType_MSR with msr-index's MSR_MTRRdefType
Use standard msr-index.h's MSR declaration and no need to declare again. [ Impact: cleanup, no object code change ] Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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committed by
H. Peter Anvin
parent
ba5673ff1f
commit
52650257ea
@@ -808,7 +808,7 @@ int __init mtrr_cleanup(unsigned address_bits)
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if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1)
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return 0;
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rdmsr(MTRRdefType_MSR, def, dummy);
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rdmsr(MSR_MTRRdefType, def, dummy);
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def &= 0xff;
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if (def != MTRR_TYPE_UNCACHABLE)
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return 0;
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@@ -1003,7 +1003,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
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*/
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if (!is_cpu(INTEL) || disable_mtrr_trim)
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return 0;
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rdmsr(MTRRdefType_MSR, def, dummy);
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rdmsr(MSR_MTRRdefType, def, dummy);
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def &= 0xff;
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if (def != MTRR_TYPE_UNCACHABLE)
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return 0;
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@@ -314,7 +314,7 @@ void __init get_mtrr_state(void)
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if (mtrr_state.have_fixed)
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get_fixed_ranges(mtrr_state.fixed_ranges);
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rdmsr(MTRRdefType_MSR, lo, dummy);
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rdmsr(MSR_MTRRdefType, lo, dummy);
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mtrr_state.def_type = (lo & 0xff);
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mtrr_state.enabled = (lo & 0xc00) >> 10;
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@@ -579,10 +579,10 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
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__flush_tlb();
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/* Save MTRR state */
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rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
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rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
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/* Disable MTRRs, and set the default type to uncached */
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mtrr_wrmsr(MTRRdefType_MSR, deftype_lo & ~0xcff, deftype_hi);
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mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
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}
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static void post_set(void) __releases(set_atomicity_lock)
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@@ -591,7 +591,7 @@ static void post_set(void) __releases(set_atomicity_lock)
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__flush_tlb();
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
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mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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@@ -5,8 +5,6 @@
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#include <linux/types.h>
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#include <linux/stddef.h>
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#define MTRRdefType_MSR 0x2ff
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#define MTRR_CHANGE_MASK_FIXED 0x01
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#define MTRR_CHANGE_MASK_VARIABLE 0x02
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#define MTRR_CHANGE_MASK_DEFTYPE 0x04
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@@ -35,7 +35,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
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if (use_intel())
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/* Save MTRR state */
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rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
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rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
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else
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/* Cyrix ARRs - everything else were excluded at the top */
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ctxt->ccr3 = getCx86(CX86_CCR3);
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@@ -46,7 +46,7 @@ void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
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{
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if (use_intel())
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/* Disable MTRRs, and set the default type to uncached */
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mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
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mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,
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ctxt->deftype_hi);
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else if (is_cpu(CYRIX))
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/* Cyrix ARRs - everything else were excluded at the top */
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@@ -64,7 +64,7 @@ void set_mtrr_done(struct set_mtrr_context *ctxt)
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/* Restore MTRRdefType */
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if (use_intel())
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
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mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
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else
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/* Cyrix ARRs - everything else was excluded at the top */
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setCx86(CX86_CCR3, ctxt->ccr3);
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