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Merge tag 'pinctrl-for-v3.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

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Pull pin control fixes from Linus Walleij:
 - Driver fixes for AM33xx, SIRF and PFC pin controllers
 - Fix a compile warning from the pinctrl single-register driver
 - Fix a little nasty memory leak

* tag 'pinctrl-for-v3.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: fix a memleak when freeing maps
  pinctrl: pinctrl-single: fix compile warning when no CONFIG_PM
  pinctrl: sh-pfc: fix SDHI0 VccQ regulator on sh73a0 with DT
  arm/dts: sirf: fix the pingroup name mismatch between drivers and dts
  pinctrl: sirf: add usp0_uart_nostreamctrl pin group for usp-uart without flowctrl
  pinctrl: sirf: fix the pin number and mux bit for usp0
  pinctrl: am33xx dt binding: correct include path
This commit is contained in:
Linus Torvalds
2013-07-28 18:19:27 -07:00
parent 6803f37e09 db6c2c69c2
commit 76d25a5f2f
7 changed files with 49 additions and 19 deletions
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22
arch/arm/boot/dts/atlas6.dtsi
View File

@@ -485,6 +485,12 @@
sirf,function = "usp0";
};
};
usp0_uart_nostreamctrl_pins_a: usp0@1 {
usp0 {
sirf,pins = "usp0_uart_nostreamctrl_grp";
sirf,function = "usp0_uart_nostreamctrl";
};
};
usp1_pins_a: usp1@0 {
usp1 {
sirf,pins = "usp1grp";
@@ -515,16 +521,16 @@
sirf,function = "pulse_count";
};
};
cko0_rst_pins_a: cko0_rst@0 {
cko0_rst {
sirf,pins = "cko0_rstgrp";
sirf,function = "cko0_rst";
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_rst_pins_a: cko1_rst@0 {
cko1_rst {
sirf,pins = "cko1_rstgrp";
sirf,function = "cko1_rst";
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};

16
arch/arm/boot/dts/prima2.dtsi
View File

@@ -515,16 +515,16 @@
sirf,function = "pulse_count";
};
};
cko0_rst_pins_a: cko0_rst@0 {
cko0_rst {
sirf,pins = "cko0_rstgrp";
sirf,function = "cko0_rst";
cko0_pins_a: cko0@0 {
cko0 {
sirf,pins = "cko0grp";
sirf,function = "cko0";
};
};
cko1_rst_pins_a: cko1_rst@0 {
cko1_rst {
sirf,pins = "cko1_rstgrp";
sirf,function = "cko1_rst";
cko1_pins_a: cko1@0 {
cko1 {
sirf,pins = "cko1grp";
sirf,function = "cko1";
};
};
};

1
drivers/pinctrl/core.c
View File

@@ -1193,6 +1193,7 @@ void pinctrl_unregister_map(struct pinctrl_map const *map)
list_for_each_entry(maps_node, &pinctrl_maps, node) {
if (maps_node->maps == map) {
list_del(&maps_node->node);
kfree(maps_node);
mutex_unlock(&pinctrl_maps_mutex);
return;
}

2
drivers/pinctrl/pinctrl-single.c
View File

@@ -1483,6 +1483,7 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
return ret;
}
#ifdef CONFIG_PM
static int pinctrl_single_suspend(struct platform_device *pdev,
pm_message_t state)
{
@@ -1505,6 +1506,7 @@ static int pinctrl_single_resume(struct platform_device *pdev)
return pinctrl_force_default(pcs->pctl);
}
#endif
static int pcs_probe(struct platform_device *pdev)
{

1
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@@ -3785,6 +3785,7 @@ static const struct regulator_desc sh73a0_vccq_mc0_desc = {
static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
};
static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {

24
drivers/pinctrl/sirf/pinctrl-atlas6.c
View File

@@ -496,7 +496,7 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = {
{
.group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
},
};
@@ -507,8 +507,21 @@ static const struct sirfsoc_padmux usp0_padmux = {
.funcval = 0,
};
static const unsigned usp0_pins[] = { 51, 52, 53, 54 };
static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
{
.group = 1,
.mask = BIT(20) | BIT(21),
},
};
static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
.muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
.muxmask = usp0_uart_nostreamctrl_muxmask,
};
static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{
.group = 0,
@@ -822,6 +835,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
usp0_uart_nostreamctrl_pins),
SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
@@ -862,6 +877,8 @@ static const char * const uart0grp[] = { "uart0grp" };
static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0_uart_nostreamctrl_grp[] = {
"usp0_uart_nostreamctrl_grp" };
static const char * const usp0grp[] = { "usp0grp" };
static const char * const usp1grp[] = { "usp1grp" };
static const char * const i2c0grp[] = { "i2c0grp" };
@@ -904,6 +921,9 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp,
usp0_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),

2
include/dt-bindings/pinctrl/am33xx.h
View File

@@ -5,7 +5,7 @@
#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
#define _DT_BINDINGS_PINCTRL_AM33XX_H
#include <include/dt-bindings/pinctrl/omap.h>
#include <dt-bindings/pinctrl/omap.h>
/* am33xx specific mux bit defines */
#undef PULL_ENA