iwlwifi: define ANA_PLL values in iwl-csr.h
This patch defines ANA_PLL values in iwl-csr.h Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville
parent
fe07aa7acd
commit
a693f187fa
@@ -1229,7 +1229,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
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iwl3945_power_init_handle(priv);
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spin_lock_irqsave(&priv->lock, flags);
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iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
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iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
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iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
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CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
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@@ -95,8 +95,7 @@
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#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
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#define CSR_LED_REG (CSR_BASE+0x094)
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/* Analog phase-lock-loop configuration (3945 only)
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* Set bit 24. */
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/* Analog phase-lock-loop configuration */
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#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
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/*
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* Indicates hardware rev, to determine CCK backoff for txpower calculation.
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@@ -219,6 +218,10 @@
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#define CSR_LED_REG_TRUN_ON (0x78)
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#define CSR_LED_REG_TRUN_OFF (0x38)
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/* ANA_PLL */
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#define CSR39_ANA_PLL_CFG_VAL (0x01000000)
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#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
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/*=== HBUS (Host-side Bus) ===*/
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#define HBUS_BASE (0x400)
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/*
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