tg3: Move tg3_nvram_write_block functions
This patch moves the tg3_nvram_write_block functions higher in the file to eliminate a prototype. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
ccd5ba9db5
commit
dbe9b92a60
@ -2978,6 +2978,256 @@ static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
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return res;
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}
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static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
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u32 offset, u32 len, u8 *buf)
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{
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int i, j, rc = 0;
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u32 val;
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for (i = 0; i < len; i += 4) {
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u32 addr;
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__be32 data;
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addr = offset + i;
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memcpy(&data, buf + i, 4);
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/*
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* The SEEPROM interface expects the data to always be opposite
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* the native endian format. We accomplish this by reversing
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* all the operations that would have been performed on the
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* data from a call to tg3_nvram_read_be32().
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*/
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tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
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val = tr32(GRC_EEPROM_ADDR);
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tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
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val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
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EEPROM_ADDR_READ);
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tw32(GRC_EEPROM_ADDR, val |
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(0 << EEPROM_ADDR_DEVID_SHIFT) |
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(addr & EEPROM_ADDR_ADDR_MASK) |
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EEPROM_ADDR_START |
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EEPROM_ADDR_WRITE);
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for (j = 0; j < 1000; j++) {
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val = tr32(GRC_EEPROM_ADDR);
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if (val & EEPROM_ADDR_COMPLETE)
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break;
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msleep(1);
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}
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if (!(val & EEPROM_ADDR_COMPLETE)) {
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rc = -EBUSY;
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break;
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}
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}
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return rc;
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}
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/* offset and length are dword aligned */
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static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
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u8 *buf)
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{
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int ret = 0;
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u32 pagesize = tp->nvram_pagesize;
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u32 pagemask = pagesize - 1;
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u32 nvram_cmd;
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u8 *tmp;
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tmp = kmalloc(pagesize, GFP_KERNEL);
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if (tmp == NULL)
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return -ENOMEM;
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while (len) {
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int j;
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u32 phy_addr, page_off, size;
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phy_addr = offset & ~pagemask;
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for (j = 0; j < pagesize; j += 4) {
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ret = tg3_nvram_read_be32(tp, phy_addr + j,
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(__be32 *) (tmp + j));
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if (ret)
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break;
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}
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if (ret)
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break;
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page_off = offset & pagemask;
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size = pagesize;
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if (len < size)
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size = len;
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len -= size;
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memcpy(tmp + page_off, buf, size);
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offset = offset + (pagesize - page_off);
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tg3_enable_nvram_access(tp);
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/*
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* Before we can erase the flash page, we need
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* to issue a special "write enable" command.
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*/
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nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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/* Erase the target page */
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tw32(NVRAM_ADDR, phy_addr);
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
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NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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/* Issue another write enable to start the write. */
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nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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for (j = 0; j < pagesize; j += 4) {
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__be32 data;
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data = *((__be32 *) (tmp + j));
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tw32(NVRAM_WRDATA, be32_to_cpu(data));
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tw32(NVRAM_ADDR, phy_addr + j);
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
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NVRAM_CMD_WR;
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if (j == 0)
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nvram_cmd |= NVRAM_CMD_FIRST;
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else if (j == (pagesize - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
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if (ret)
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break;
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}
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if (ret)
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break;
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}
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nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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tg3_nvram_exec_cmd(tp, nvram_cmd);
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kfree(tmp);
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return ret;
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}
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/* offset and length are dword aligned */
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static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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u8 *buf)
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{
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int i, ret = 0;
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for (i = 0; i < len; i += 4, offset += 4) {
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u32 page_off, phy_addr, nvram_cmd;
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__be32 data;
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memcpy(&data, buf + i, 4);
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tw32(NVRAM_WRDATA, be32_to_cpu(data));
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page_off = offset % tp->nvram_pagesize;
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phy_addr = tg3_nvram_phys_addr(tp, offset);
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tw32(NVRAM_ADDR, phy_addr);
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
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if (page_off == 0 || i == 0)
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nvram_cmd |= NVRAM_CMD_FIRST;
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if (page_off == (tp->nvram_pagesize - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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if (i == (len - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
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!tg3_flag(tp, 5755_PLUS) &&
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(tp->nvram_jedecnum == JEDEC_ST) &&
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(nvram_cmd & NVRAM_CMD_FIRST)) {
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u32 cmd;
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cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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ret = tg3_nvram_exec_cmd(tp, cmd);
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if (ret)
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break;
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}
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if (!tg3_flag(tp, FLASH)) {
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/* We always do complete word writes to eeprom. */
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nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
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}
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ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
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if (ret)
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break;
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}
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return ret;
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}
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/* offset and length are dword aligned */
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static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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{
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int ret;
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if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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udelay(40);
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}
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if (!tg3_flag(tp, NVRAM)) {
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ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
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} else {
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u32 grc_mode;
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ret = tg3_nvram_lock(tp);
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if (ret)
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return ret;
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tg3_enable_nvram_access(tp);
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if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
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tw32(NVRAM_WRITE1, 0x406);
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grc_mode = tr32(GRC_MODE);
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tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
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if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
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ret = tg3_nvram_write_block_buffered(tp, offset, len,
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buf);
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} else {
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ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
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buf);
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}
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grc_mode = tr32(GRC_MODE);
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tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
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tg3_disable_nvram_access(tp);
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tg3_nvram_unlock(tp);
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}
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if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
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udelay(40);
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}
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return ret;
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}
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#define RX_CPU_SCRATCH_BASE 0x30000
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#define RX_CPU_SCRATCH_SIZE 0x04000
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#define TX_CPU_SCRATCH_BASE 0x34000
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@ -10147,8 +10397,6 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
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return 0;
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}
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static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
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static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
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{
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struct tg3 *tp = netdev_priv(dev);
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@ -12745,254 +12993,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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}
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}
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static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
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u32 offset, u32 len, u8 *buf)
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{
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int i, j, rc = 0;
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u32 val;
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for (i = 0; i < len; i += 4) {
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u32 addr;
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__be32 data;
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addr = offset + i;
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memcpy(&data, buf + i, 4);
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/*
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* The SEEPROM interface expects the data to always be opposite
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* the native endian format. We accomplish this by reversing
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* all the operations that would have been performed on the
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* data from a call to tg3_nvram_read_be32().
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*/
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tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
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val = tr32(GRC_EEPROM_ADDR);
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tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
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val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
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EEPROM_ADDR_READ);
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tw32(GRC_EEPROM_ADDR, val |
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(0 << EEPROM_ADDR_DEVID_SHIFT) |
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(addr & EEPROM_ADDR_ADDR_MASK) |
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EEPROM_ADDR_START |
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EEPROM_ADDR_WRITE);
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for (j = 0; j < 1000; j++) {
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val = tr32(GRC_EEPROM_ADDR);
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if (val & EEPROM_ADDR_COMPLETE)
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break;
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msleep(1);
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}
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if (!(val & EEPROM_ADDR_COMPLETE)) {
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rc = -EBUSY;
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break;
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}
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}
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return rc;
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}
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/* offset and length are dword aligned */
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static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
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u8 *buf)
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{
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int ret = 0;
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u32 pagesize = tp->nvram_pagesize;
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u32 pagemask = pagesize - 1;
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u32 nvram_cmd;
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u8 *tmp;
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tmp = kmalloc(pagesize, GFP_KERNEL);
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if (tmp == NULL)
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return -ENOMEM;
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while (len) {
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int j;
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u32 phy_addr, page_off, size;
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phy_addr = offset & ~pagemask;
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for (j = 0; j < pagesize; j += 4) {
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ret = tg3_nvram_read_be32(tp, phy_addr + j,
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(__be32 *) (tmp + j));
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if (ret)
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break;
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}
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if (ret)
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break;
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page_off = offset & pagemask;
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size = pagesize;
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if (len < size)
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size = len;
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len -= size;
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memcpy(tmp + page_off, buf, size);
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offset = offset + (pagesize - page_off);
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tg3_enable_nvram_access(tp);
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/*
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* Before we can erase the flash page, we need
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* to issue a special "write enable" command.
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*/
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nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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/* Erase the target page */
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tw32(NVRAM_ADDR, phy_addr);
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
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NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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/* Issue another write enable to start the write. */
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nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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if (tg3_nvram_exec_cmd(tp, nvram_cmd))
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break;
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for (j = 0; j < pagesize; j += 4) {
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__be32 data;
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data = *((__be32 *) (tmp + j));
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tw32(NVRAM_WRDATA, be32_to_cpu(data));
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tw32(NVRAM_ADDR, phy_addr + j);
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
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NVRAM_CMD_WR;
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if (j == 0)
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nvram_cmd |= NVRAM_CMD_FIRST;
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else if (j == (pagesize - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
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break;
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}
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if (ret)
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break;
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}
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nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
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tg3_nvram_exec_cmd(tp, nvram_cmd);
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kfree(tmp);
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return ret;
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}
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/* offset and length are dword aligned */
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static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
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u8 *buf)
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{
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int i, ret = 0;
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for (i = 0; i < len; i += 4, offset += 4) {
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u32 page_off, phy_addr, nvram_cmd;
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__be32 data;
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memcpy(&data, buf + i, 4);
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tw32(NVRAM_WRDATA, be32_to_cpu(data));
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page_off = offset % tp->nvram_pagesize;
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phy_addr = tg3_nvram_phys_addr(tp, offset);
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tw32(NVRAM_ADDR, phy_addr);
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nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
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if (page_off == 0 || i == 0)
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nvram_cmd |= NVRAM_CMD_FIRST;
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if (page_off == (tp->nvram_pagesize - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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if (i == (len - 4))
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nvram_cmd |= NVRAM_CMD_LAST;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
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!tg3_flag(tp, 5755_PLUS) &&
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(tp->nvram_jedecnum == JEDEC_ST) &&
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(nvram_cmd & NVRAM_CMD_FIRST)) {
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if ((ret = tg3_nvram_exec_cmd(tp,
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NVRAM_CMD_WREN | NVRAM_CMD_GO |
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NVRAM_CMD_DONE)))
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break;
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}
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if (!tg3_flag(tp, FLASH)) {
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/* We always do complete word writes to eeprom. */
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nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
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}
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if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
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break;
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}
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return ret;
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}
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/* offset and length are dword aligned */
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static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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{
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int ret;
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if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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udelay(40);
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||||
}
|
||||
|
||||
if (!tg3_flag(tp, NVRAM)) {
|
||||
ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
|
||||
} else {
|
||||
u32 grc_mode;
|
||||
|
||||
ret = tg3_nvram_lock(tp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
tg3_enable_nvram_access(tp);
|
||||
if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
|
||||
tw32(NVRAM_WRITE1, 0x406);
|
||||
|
||||
grc_mode = tr32(GRC_MODE);
|
||||
tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
|
||||
|
||||
if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
|
||||
ret = tg3_nvram_write_block_buffered(tp, offset, len,
|
||||
buf);
|
||||
} else {
|
||||
ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
|
||||
buf);
|
||||
}
|
||||
|
||||
grc_mode = tr32(GRC_MODE);
|
||||
tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
|
||||
|
||||
tg3_disable_nvram_access(tp);
|
||||
tg3_nvram_unlock(tp);
|
||||
}
|
||||
|
||||
if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
|
||||
tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
|
||||
udelay(40);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct subsys_tbl_ent {
|
||||
u16 subsys_vendor, subsys_devid;
|
||||
u32 phy_id;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user