serial: sh-sci: Generalize overrun handling.
This consolidates all of the broken out overrun handling and ensures that we have sensible defaults per-port type, in addition to making sure that overruns are flagged appropriately in the error mask for parts that haven't explicitly disabled support for it. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
b030340161
commit
debf950716
@ -563,13 +563,19 @@ static int sci_handle_errors(struct uart_port *port)
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int copied = 0;
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unsigned short status = sci_in(port, SCxSR);
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struct tty_struct *tty = port->state->port.tty;
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struct sci_port *s = to_sci_port(port);
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if (status & SCxSR_ORER(port)) {
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/* overrun error */
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if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
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copied++;
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/*
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* Handle overruns, if supported.
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*/
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if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
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if (status & (1 << s->cfg->overrun_bit)) {
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/* overrun error */
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if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
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copied++;
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dev_notice(port->dev, "overrun error");
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dev_notice(port->dev, "overrun error");
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}
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}
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if (status & SCxSR_FER(port)) {
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@ -617,12 +623,19 @@ static int sci_handle_errors(struct uart_port *port)
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static int sci_handle_fifo_overrun(struct uart_port *port)
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{
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struct tty_struct *tty = port->state->port.tty;
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struct sci_port *s = to_sci_port(port);
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int copied = 0;
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/*
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* XXX: Technically not limited to non-SCIFs, it's simply the
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* SCLSR check that is for the moment SCIF-specific. This
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* probably wants to be revisited for SCIFA/B as well as for
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* factoring in SCI overrun detection.
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*/
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if (port->type != PORT_SCIF)
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return 0;
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if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
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if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
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sci_out(port, SCLSR, 0);
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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@ -1755,6 +1768,32 @@ static int __devinit sci_init_single(struct platform_device *dev,
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sci_port->break_timer.function = sci_break_timer;
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init_timer(&sci_port->break_timer);
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/*
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* Establish some sensible defaults for the error detection.
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*/
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if (!p->error_mask)
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p->error_mask = (p->type == PORT_SCI) ?
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SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
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/*
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* Establish sensible defaults for the overrun detection, unless
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* the part has explicitly disabled support for it.
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*/
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if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
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if (p->type == PORT_SCI)
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p->overrun_bit = 5;
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else if (p->scbrr_algo_id == SCBRR_ALGO_4)
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p->overrun_bit = 9;
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else
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p->overrun_bit = 0;
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/*
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* Make the error mask inclusive of overrun detection, if
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* supported.
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*/
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p->error_mask |= (1 << p->overrun_bit);
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}
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sci_port->cfg = p;
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port->mapbase = p->mapbase;
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@ -19,11 +19,9 @@
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defined(CONFIG_ARCH_SH7372)
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# define PORT_PTCR 0xA405011EUL
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# define PORT_PVCR 0xA4050122UL
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# define SCIF_ORER 0x0200 /* overrun error bit */
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#elif defined(CONFIG_SH_RTS7751R2D)
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# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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@ -32,15 +30,12 @@
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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# define SCSPTR1 0xffe0001c /* 8 bit SCI */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define PACR 0xa4050100
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# define PBCR 0xa4050102
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
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@ -48,35 +43,24 @@
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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# define PWDR 0xA4050166
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# define PSCR 0xA405011E
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCSPTR0 SCPDR0
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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# define SCSPTR0 0xa4050160
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
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# define SCSPTR0 0xfe4b0020
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# define SCIF_ORER 0x0001
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
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# define SCSPTR0 0xff923020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)
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# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
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defined(CONFIG_CPU_SUBTYPE_SH7203) || \
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defined(CONFIG_CPU_SUBTYPE_SH7206) || \
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@ -84,36 +68,12 @@
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# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
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# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* Overrun error bit */
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#else
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# error CPU subtype not defined
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#endif
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/* SCxSR SCI */
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#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
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#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
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/* SCxSR SCIF */
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#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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@ -121,35 +81,27 @@
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372)
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# define SCIF_ORER 0x0200
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# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
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# define SCIF_RFDC_MASK 0x007f
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# define SCIF_TXROOM_MAX 64
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
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# define SCIF_RFDC_MASK 0x007f
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# define SCIF_TXROOM_MAX 64
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/* SH7763 SCIF2 support */
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# define SCIF2_RFDC_MASK 0x001f
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# define SCIF2_TXROOM_MAX 16
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#else
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# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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# define SCIF_RFDC_MASK 0x001f
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# define SCIF_TXROOM_MAX 16
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#endif
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#ifndef SCIF_ORER
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#define SCIF_ORER 0x0000
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#endif
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#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
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#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
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#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
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#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
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#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
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#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
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#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
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#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
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#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask)
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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@ -8,6 +8,8 @@
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* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
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*/
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#define SCIx_NOT_SUPPORTED (-1)
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enum {
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SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
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SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
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@ -25,6 +27,28 @@ enum {
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#define SCSCR_CKE1 (1 << 1)
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#define SCSCR_CKE0 (1 << 0)
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/* SCxSR SCI */
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#define SCI_TDRE 0x80
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#define SCI_RDRF 0x40
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#define SCI_ORER 0x20
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#define SCI_FER 0x10
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#define SCI_PER 0x08
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#define SCI_TEND 0x04
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
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/* SCxSR SCIF */
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#define SCIF_ER 0x0080
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#define SCIF_TEND 0x0040
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#define SCIF_TDFE 0x0020
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#define SCIF_BRK 0x0010
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#define SCIF_FER 0x0008
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#define SCIF_PER 0x0004
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#define SCIF_RDF 0x0002
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#define SCIF_DR 0x0001
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
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/* Offsets into the sci_port->irqs array */
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enum {
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SCIx_ERI_IRQ,
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@ -56,6 +80,12 @@ struct plat_sci_port {
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unsigned int scbrr_algo_id; /* SCBRR calculation algo */
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unsigned int scscr; /* SCSCR initialization */
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/*
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* Platform overrides if necessary, defaults otherwise.
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*/
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int overrun_bit;
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unsigned int error_mask;
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struct device *dma_dev;
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unsigned int dma_slave_tx;
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